Example Of Two-Cycle Single Transfer Timing (Between External Srams Connected To Nt85E500) - Renesas NU85E Preliminary User's Manual

Figure 7-30. Example of Two-Cycle Single Transfer Timing (Between External SRAMs Connected to NT85E500)
VBCLK (Input)
VMTTYP1, VMTTYP0
(Output)
VMA27 to VMA0 (Output)
VBDI31 to VBDI0 (Input)
VBDO31 to VBDO0 (Output)
VMSTZ (Output)
VMWRITE (Output)
VMBENZ3 to VMBENZ0
(Output)
VMCTYP2 to VMCTYP0
(Output)
VMSEQ2 to VMSEQ0
(Output)
VMSIZE1, VMSIZE0
(Output)
VMLOCK (Output)
VBDC (Output)
VBDV (Output)
VDCSZ7 to VDCSZ0
(Output)
VMWAIT (Input)
VMAHLD (Input)
VMLAST (Input)
DMARQn (Input)
DMACTVn (Output)
DMTCOn (Output)
A25 to A0 (Output) Note
DI31 to DI0 (Input) Note
DO31 to DO0 (Output) Note
RDZ (Output) Note
WRZ3 to WRZ0 (Output) Note
CSZ7 to CSZ0 (Output) Note
Note These are NT85E500 signals.
2-cycle single transfer
Read cycle Write cycle
0H 2H 3H 0H 2H 3H
FH 0H FH 0H
6H 6H
0H 0H
2H 2H
FFH FBH FFH FBH
L
L
FH 0H
FFH FBH FFH FBH
CPU cycle 2-cycle single transfer
Read cycle Write cycle
0H 2H 3H 0H 2H
FH 0H FH
6H
0H
2H
FFH FBH FFH
FH
FFH FBH FFH
3H 0H
0H FH
6H
0H
2H
FBH FFH
0H FH
FBH FFH