Register Direct-Rn; Register Indirect-@Ern; Register Indirect With Displacement-@(D:2, Ern), @(D:16, Ern), Or @(D:32, Ern) - Renesas H8SX/1500 Series Hardware Manual

2.8.1 Register Direct—Rn
The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the
register field in the instruction code.
R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers.
ER0 to ER7 can be specified as 32-bit registers.
2.8.2 Register Indirect—@ERn
The operand value is the contents of the memory location which is pointed to by the contents of an
address register (ERn). ERn is specified by the register field of the instruction code.
In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are
valid and the upper 8 bits are all assumed to be 0 (H'00).
2.8.3 Register Indirect with Displacement—@(d:2, ERn), @(d:16, ERn), or
@(d:32, ERn)
The operand value is the contents of a memory location which is pointed to by the sum of the
contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the
register field of the instruction code. The displacement is included in the instruction code and the
16-bit displacement is sign-extended when added to ERn.
This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the
displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the
operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data.
Rev. 3.00 Mar. 14, 2006 Page 55 of 804
REJ09B0104-0300
Section 2 CPU