Hardware Interrupt Nmi - Texas Instruments TMS320C28x Reference Manual

3.5.3

Hardware Interrupt NMI

The CPU clears LOOP, EALLOW, and IDLESTAT so that the ISR operates
within a new context.
8) Load PC with fetched vector. The PC is loaded with the interrupt vector
that was fetched in step 4. The vector forces program control to the ISR.
9) Execute interrupt service routine. The CPU executes the program code
you have prepared to handle the interrupt. You may wish to have the inter-
rupt service routine (ISR) save register values in addition to those saved
in step 6. A typical ISR is shown in Example 3−1 on page 3-16.
If you want the ISR to inform external hardware that the interrupt is being
serviced, you can use the IACK instruction to send an interrupt acknowl-
edge signal. The IACK instruction accepts a 16-bit constant as an operand
and drives this 16-bit value on the 16 least significant lines of the data-write
bus, DWDB(15:0). For a detailed description of the IACK instruction, see
Chapter 6, C28x Assembly Language Instructions.
10) Program continues. After the interrupt service routine is completed, the
program continues where it left off (at the return address).
An interrupt can be requested by way the NMI input pin, which must be driven
low to initiate the interrupt. Although NMI cannot be masked, there are some
debug execution states in which NMI is not serviced (see section 7.4,
Execution Control Modes, on page 7-7). For more details on real-time mode,
see section 7.4.2 on page 7-9. Once a valid request is detected on the NMI pin,
the CPU handles the interrupt in the same manner as shown for the TRAP
instruction (see section 3.5.2).
Nonmaskable Interrupts
CPU Interrupts and Reset 3-21