Acm Event Interrupt Mask (Acm_Imsk) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

ACM Event Interrupt Mask (ACM_IMSK) Register

The ACM Interrupt Mask register selectively enables the interrupts associ-
ated with an event completion. When an
generated whenever Event x status (
example, interrupt on Event x completion).
ACM Event Interrupt Mask Register (ACM_IMSK)
IE15 (Evt15 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE14 (Evt14 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE13 (Evt13 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE12 (Evt12 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE11 (Evt11 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE10 (Evt10 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE9 (Evt9 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE8 (Evt8 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
Figure 22-19. ACM Event Interrupt Mask (ACM_IMSK) Register
ADSP-BF50x Blackfin Processor Hardware Reference
ESx
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
ADC Control Module (ACM)
bit is set (=1), an interrupt is
IEx
in the register) gets set (for
ACM_ES
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 Reset = 0x0000
IE0 (Evt0 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE1 (Evt1 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE2 (Evt2 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE3 (Evt3 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE4 (Evt4 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE5 (Evt5 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE6 (Evt6 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
IE7 (Evt7 Status IRQ Enable)
0 - Disable (mask interrupt)
1 - Enable (unmask interrupt)
22-35