Single Block Boot Streams - Analog Devices ADSP-BF506F Hardware Reference Manual

boot kernel provides options to execute an
instruction instead. The default behavior can be changed by an initcode
routine. The
EVT1
the
BFLAG_FIRST
learn how the application can take control.
Before the boot kernel passes program control to the application it does
some housekeeping. Most of the registers that were used are changed back
to their default state but some register values may differ for individual
boot modes. DMA configuration registers and primary register control
registers (
UARTx_LCR
posely not restored. For example
remain unchanged so that settings obtained during the booting process are
not lost.

Single Block Boot Streams

The simplest boot stream consists of a single block header and one contig-
uous block of instructions. With appropriate flag instructions the boot
kernel loads the block to the target address and immediately terminates by
executing the loaded block.
Table 24-5 shows an example of a single block boot stream header that
could be loaded from any serial boot mode. It places a 256-byte block of
instructions at L1 instruction SRAM address 0xFFA0 0000. The flags
and
BFLAG_FIRST
flags, such as
BFLAG_IGNORE
, do not make sense in this context and should not be used.
BFLAG_FILL
Table 24-5. Header for a Single Block Boot Stream
Field
BLOCK CODE
TARGET ADDRESS 0xFFA0 0000
ADSP-BF50x Blackfin Processor Hardware Reference
register is updated by the boot kernel when processing
block. See "Servicing Reset Interrupts" on page 24-8
, , etc.) are restored, while others are pur-
SPIx_CTL
SPIx_BAUD
are both set at the same time. Advanced
BFLAG_FINAL
,
BFLAG_INIT
Value Comments
0xAD33 C001 0xAD00 0000 | XORSUM | BFLAG_FINAL |
BFLAG_FIRST | (DMACODE & 0x1)
Start address of block and application code
System Reset and Booting
instruction or a
RTS
, and
UARTx_DLH
,
BFLAG_CALLBACK
RAISE 1
to
UARTx_DLL
and
24-21