Analog Devices ADSP-BF506F Hardware Reference Manual page 1108

Reset and Power-up
Table 24-2. Resets (Cont'd)
Reset Source
System soft- Calling the
ware reset
bfrom_SysControl()
tine with the
SYSCTRL_SYSRESET
triggers a system reset.
Watchdog Programming the watchdog
timer reset timer causes a watchdog timer
reset.
Core A core double fault occurs
double-fault when an exception happens
reset while the exception handler is
executing. If the core enters a
double-fault state, and the
Core Double Fault Reset
Enable bit (
set in the
a software reset will occur.
Software reset This reset is caused by execut-
ing a
by setting the software reset
(
SYSRST
debug control register
(
DBGCTL
software through the JTAG
port. The
not visible to the memory
map.
24-4
rou-
option
) is
DOUBLE_FAULT
register, then
SWRST
instruction or
RAISE 1
) bit in the core
) through emulation
register is
DBGCTL
ADSP-BF50x Blackfin Processor Hardware Reference
Result
Resets only the peripherals, excluding the RTC
(real time clock) block and most of the DPMC.
The system software reset clears bits [15:13] and
bits [11:4] of the
SYSCR
bit. The core is not reset and a boot
WURESET
sequence is not triggered. Sequencing continues
at the instruction after
bfrom_SysControl()
returns.
Resets both the core and the peripherals, exclud-
ing the RTC block and most of the DPMC.
(Because of the partial reset to the DPMC, the
watchdog timer reset is not functional when the
processor is in Sleep or Deep Sleep modes.)
The or the
SWRST SYSCR
determine whether the reset source was the
watchdog timer.
Resets both the core and the peripherals, exclud-
ing the RTC block and most of the DPMC. The
or registers can be read to deter-
SWRST SYSCR
mine whether the reset source was a core dou-
ble-fault.
Program executions vector to the 0xEF00 0000
address. The boot code executes an immediate
system reset to ensure system consistency.
register, but not the
register can be read to