Acm Timing Configuration 0 (Acm_Tc0) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

ACM Registers

ACM Timing Configuration 0 (ACM_TC0) Register

The register determines the frequency of ACLK (using the
ACM_TC0
field) and the setup cycles (using the
that the setup cycles are specified in terms of SCLK.
ACM Timing Configuration 0 Register (ACM_TC0)
15 14 13 12 11 10
0 0
SC (Setup Cycle)
ADC control (A[2:0], SGLDIFF,RANGE, and
others) setup in SCLK cycles with respect to
active CS edge:
0000 0000 – 1 SCLK cycle setup time
0000 0001 – 2 SCLK cycle setup time
...
...
1111 1111 – 256 SCLK cycle setup time
Figure 22-24. ACM Timing Configuration 0 (ACM_TC0) Register
The frequency of an internally generated clock is a function of the system
clock frequency (SCLK) and the value of the
ACLK frequency = (SCLK frequency)/(2 x (
The maximum ACLK frequency is SCLK/2, and the minimum ACLK fre-
quency is SCLK/512. So, for a 100 MHz SCLK, the ACLK range is from
195 KHz to 50 MHz.
22-40
9 8 7 6
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
field) for the ADC controls. Note
SC
5 4 3 2 1 0
Reset = 0x0000
0 0 0 0 0 0
CKDIV (Clock Divisor)
8-bit serial clock divide
modulus
field as follows:
CKDIV
+ 1))
CKDIV
CKDIV