Analog Devices ADSP-BF506F Hardware Reference Manual page 1110

Reset and Power-up

In order to perform a system reset, the
tine must be called while executing from L1 memory (either as
cache or as SRAM). When L1 instruction memory is configured as
cache, make sure the system reset sequence is read into the cache.
After either the watchdog or system software reset is initiated, the proces-
sor ensures that all asynchronous peripherals have recognized and
completed a reset.
For a reset generated by formatting the watchdog timer, the processor
transitions into the boot mode sequence. The boot mode is configured by
the state of the
A software reset is initiated by executing the
the software reset (
( is not visible to the memory map) through emulation software
DBGCTL
through the JTAG port.
A software reset only affects the state of the core. The boot kernel immedi-
ately issues a system reset to keep consistency with the system domain.
On a hardware reset, the boot kernel initializes the
0xFFA0 0000. When the booting process completes, the boot kernel
jumps to the location provided by the
the register is overwritten by the
EVT1
block of the applied boot stream. If the
set to 1 (no boot option), the
kernel on software resets. Therefore, programs can control the reset vector
for software resets through the
the flow chart in
The content of the
24-6
bit field in the
BMODE
) bit in the core debug control register (
SYSRST
EVT1
EVT1
Figure 24-1.
register may be undefined in emulator sessions.
EVT1
ADSP-BF50x Blackfin Processor Hardware Reference
bfrom_SysControl()
register.
SYSCR
instruction or setting
RAISE 1
EVT1
vector register. The content of
EVT1
TARGET ADDRESS
field of the
BCODE
register is not modified by the boot
register. This process is illustrated by
rou-
)
DBGCTL
register to
field of the first
register is
SYSCR