Acm Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

Figure 22-15. SPORT and ACM Bit Settings for ADC Applications
Bit Setting
ACM_TC0.SC
ACM_TC0.CKDIV

Control bits and registers not covered in the table should be pro-
grammed according to application requirements.

ACM Registers

The ADC controller module has a number of memory-mapped registers
(MMRs) that regulate its operation. These registers are ACM control reg-
ister ( ), ACM timing configuration registers (
ACM_CTL
status register (
interrupt mask register (
( ), ACM event missed interrupt mask register (
ACM_MS
event control registers (
( ).
ACM_ETx
Descriptions and bit diagrams for each of these MMRs are provided in the
following sections.
ADSP-BF50x Blackfin Processor Hardware Reference
Description
Setup cycles should be programmed accord-
ing to acquisition time requirements of the
ADC as specified in the data sheet.
ACM-generated clock rate should not exceed
the maximum clock supported by ADC.
), ACM event status register (
ACM_STAT
ACM_IMSK
), and ACM event time registers
ACM_ERx
ADC Control Module (ACM)
), ACM missed event status register
), ACM
ACM_TCx
), ACM
ACM_ES
), ACM
ACM_EMSK
22-31