Contents
DMA Start Address Registers
(DMAx_START_ADDR/MDMA_yy_START_ADDR) . 7-75
DMA Current Address Registers
(DMAx_CURR_ADDR/MDMA_yy_CURR_ADDR) ... 7-76
DMA Inner Loop Count Registers
(DMAx_X_COUNT/MDMA_yy_X_COUNT) ............. 7-76
DMA Current Inner Loop Count Registers
(DMAx_CURR_X_COUNT
/MDMA_yy_CURR_X_COUNT) ................................ 7-77
DMA Inner Loop Address Increment Registers
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY) ........... 7-78
DMA Outer Loop Count Registers
(DMAx_Y_COUNT/MDMA_yy_Y_COUNT) ............. 7-79
DMA Current Outer Loop Count Registers
(DMAx_CURR_Y_COUNT/
MDMA_yy_CURR_Y_COUNT) .................................. 7-80
DMA Outer Loop Address Increment Registers
(DMAx_Y_MODIFY/MDMA_yy_Y_MODIFY) ........... 7-80
DMA Next Descriptor Pointer Registers
(DMAx_NEXT_DESC_PTR/
MDMA_yy_NEXT_DESC_PTR) .................................. 7-81
DMA Current Descriptor Pointer Registers
(DMAx_CURR_DESC_PTR/
MDMA_yy_CURR_DESC_PTR) ................................. 7-82
HMDMA Registers ............................................................... 7-83
Handshake MDMA Control Registers
(HMDMAx_CONTROL) ............................................. 7-83
Handshake MDMA Initial Block Count Registers
(HMDMAx_BCINIT) ................................................... 7-86
xiv
ADSP-BF50x Blackfin Processor Hardware Reference
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