Analog Devices ADSP-BF506F Hardware Reference Manual page 15

Handshake MDMA Current Block Count Registers
(HMDMAx_BCOUNT) ................................................ 7-86
Handshake MDMA Current Edge Count Registers
(HMDMAx_ECOUNT) ................................................ 7-87
Handshake MDMA Initial Edge Count Registers
(HMDMAx_ECINIT) ................................................... 7-88
Handshake MDMA Edge Count Urgent Registers
(HMDMAx_ECURGENT) ............................................ 7-88
Handshake MDMA Edge Count Overflow Interrupt
Registers (HMDMAx_ECOVERFLOW) ........................ 7-89
DMA Traffic Control Registers
(DMA_TC_PER and DMA_TC_CNT) .............................. 7-89
DMA_TC_PER Register ................................................... 7-90
DMA_TC_CNT Register .................................................. 7-90
Programming Examples ............................................................... 7-92
Register-Based 2-D Memory DMA ........................................ 7-92
Initializing Descriptors in Memory ........................................ 7-95
Software-Triggered Descriptor Fetch Example ........................ 7-98
Handshaked Memory DMA Example ................................... 7-101
Unique Information for the ADSP-BF50x Processor .................. 7-103
Static Channel Prioritization ................................................ 7-105
DYNAMIC POWER MANAGEMENT
Phase Locked Loop and Clock Control .......................................... 8-1
PLL Overview ......................................................................... 8-2
PLL Clock Multiplier Ratios .................................................... 8-4
Core Clock/System Clock Ratio Control ............................. 8-5
ADSP-BF50x Blackfin Processor Hardware Reference
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