Analog Devices ADSP-BF506F Hardware Reference Manual page 13

DMA Performance ................................................................ 7-41
DMA Throughput ............................................................ 7-42
Memory DMA Timing Details .......................................... 7-45
Static Channel Prioritization ............................................. 7-45
Temporary DMA Urgency ................................................. 7-45
Memory DMA Priority and Scheduling ............................. 7-47
Traffic Control .................................................................. 7-49
Programming Model ................................................................... 7-51
Synchronization of Software and DMA .................................. 7-51
Single-Buffer DMA Transfers ............................................. 7-53
Continuous Transfers Using Autobuffering ........................ 7-54
Descriptor Structures ........................................................ 7-56
Descriptor Queue Management ......................................... 7-57
Descriptor Queue Using Interrupts on Every
Descriptor .................................................................. 7-58
Descriptor Queue Using Minimal Interrupts .................. 7-59
Software-Triggered Descriptor Fetches ............................... 7-61
DMA Registers ........................................................................... 7-63
DMA Channel Registers ........................................................ 7-64
DMA Peripheral Map Registers
(DMAx_PERIPHERAL_MAP/
MDMA_yy_PERIPHERAL_MAP) ................................. 7-67
DMA Configuration Registers
(DMAx_CONFIG/MDMA_yy_CONFIG) .................... 7-68
DMA Interrupt Status Registers
(DMAx_IRQ_STATUS/MDMA_yy_IRQ_STATUS) ...... 7-72
ADSP-BF50x Blackfin Processor Hardware Reference
Contents
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