Analog Devices ADSP-BF506F Hardware Reference Manual page 9

Program Suspend Status Bit (SR2) .................................... 6-22
Block Protection Status Bit (SR1) ..................................... 6-22
Bank Write Status Bit (SR0) ............................................. 6-22
Configuration Register ......................................................... 6-24
Read Select Bit (CR15) .................................................... 6-24
X Latency Bits (CR13-CR11) ........................................... 6-25
Wait Polarity Bit (CR10) .................................................. 6-25
Data Output Configuration Bit (CR9) ............................. 6-26
Wait Configuration Bit (CR8) .......................................... 6-27
Burst Type Bit (CR7) ....................................................... 6-27
Valid Clock Edge Bit (CR6) ............................................. 6-27
Wrap Burst Bit (CR3) ...................................................... 6-27
Burst Length Bits (CR2-CR0) .......................................... 6-27
Read Modes ......................................................................... 6-33
Asynchronous Read Mode ................................................ 6-33
Synchronous Burst Read Mode ......................................... 6-33
Synchronous Burst Read Suspend ..................................... 6-35
Single Synchronous Read Mode ........................................ 6-36
Dual Operations and Multiple Bank Architecture .................. 6-36
ADSP-BF50x Blackfin Processor Hardware Reference
Contents
ix