Texas Instruments AFE79 Series User Manual

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User's Guide
AFE79xx SPI Bringup Guide With Xilinx FPGAs
This tutorial guides through the process of using Xilinx Vivado and Vitis development environments along
with Texas Instruments supplied custom IP to bring up Serial Peripheral Interface (SPI) and non-timing critical
General-Purpose Outputs (GPOs) for Texas Instruments AFE79xx EVM along with the companion LMK series
clocking chip, thereby enabling an easier integration of the AFE79xx device into a system design. This guide will
demonstrate how to use a Xilinx ZCU102 setup as an example.
1 Introduction.............................................................................................................................................................................2
2 Prerequisites...........................................................................................................................................................................
3 Typical Bare-Metal Design Flow............................................................................................................................................
4 Background.............................................................................................................................................................................4
5 AFE SPI IP Container Pinout..................................................................................................................................................5
6 TI AFE SPI IP Container..........................................................................................................................................................6
7 Create Block Designs With TI AFE SPI
8 Create New Platforms in Vitis .............................................................................................................................................
9 Create New Application Projects in
10 Build Application Projects.................................................................................................................................................
11 Configure the AXI GPIO......................................................................................................................................................19
11.1 Initializing the GPIO........................................................................................................................................................19
11.2 Setting the Direction.......................................................................................................................................................
11.3 Setting High or Low for Corresponding Bits...................................................................................................................
12 Configure the AXI SPI.........................................................................................................................................................20
13 Create Boot Images to Run on SD Card...........................................................................................................................
14 Set up and Power on Hardware.........................................................................................................................................23
15 Set up ZCU102 Board Interface for VADJ_FMC...............................................................................................................
16 Debug Application Projects and Set up Vitis Serial Terminal........................................................................................
17 Execute the Application.....................................................................................................................................................
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SBAU412 - NOVEMBER 2022
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ABSTRACT

Table of Contents

IP.............................................................................................................................7
Vitis............................................................................................................................14
Copyright © 2022 Texas Instruments Incorporated
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AFE79xx SPI Bringup Guide With Xilinx FPGAs
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