Texas Instruments AFE79 Series User Manual
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Texas Instruments AFE79 Series User Manual

Spi bringup guide with xilinx fpgas
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User's Guide
AFE79xx SPI Bringup Guide With Xilinx FPGAs
This tutorial guides through the process of using Xilinx Vivado and Vitis development environments along
with Texas Instruments supplied custom IP to bring up Serial Peripheral Interface (SPI) and non-timing critical
General-Purpose Outputs (GPOs) for Texas Instruments AFE79xx EVM along with the companion LMK series
clocking chip, thereby enabling an easier integration of the AFE79xx device into a system design. This guide will
demonstrate how to use a Xilinx ZCU102 setup as an example.
1
Introduction.............................................................................................................................................................................2
2 Prerequisites...........................................................................................................................................................................
3 Typical Bare-Metal Design Flow............................................................................................................................................
4
Background.............................................................................................................................................................................4
Pinout..................................................................................................................................................5
Container..........................................................................................................................................................6
8 Create New Platforms in Vitis .............................................................................................................................................
10 Build Application Projects.................................................................................................................................................
GPIO......................................................................................................................................................19
GPIO........................................................................................................................................................19
11.2 Setting the Direction.......................................................................................................................................................
11.3 Setting High or Low for Corresponding Bits...................................................................................................................
SPI.........................................................................................................................................................20
13 Create Boot Images to Run on SD Card...........................................................................................................................
Hardware.........................................................................................................................................23
15 Set up ZCU102 Board Interface for VADJ_FMC...............................................................................................................
16 Debug Application Projects and Set up Vitis Serial Terminal........................................................................................
17 Execute the Application.....................................................................................................................................................
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SBAU412 - NOVEMBER 2022
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ABSTRACT

Table of Contents

IP.............................................................................................................................7
Vitis............................................................................................................................14
Copyright © 2022 Texas Instruments Incorporated
Table of Contents
AFE79xx SPI Bringup Guide With Xilinx FPGAs
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Summary of Contents for Texas Instruments AFE79 Series

  • Page 1: Table Of Contents

    This tutorial guides through the process of using Xilinx Vivado and Vitis development environments along with Texas Instruments supplied custom IP to bring up Serial Peripheral Interface (SPI) and non-timing critical General-Purpose Outputs (GPOs) for Texas Instruments AFE79xx EVM along with the companion LMK series clocking chip, thereby enabling an easier integration of the AFE79xx device into a system design.

  • Page 2: Introduction

    2 RX lanes (1RX, 1FB) and 2 TX lanes at 5 Gbps AFE EVM AFE79xx EVM FPGA Board Xilinx ZCU102 EVM AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 3: Typical Bare-Metal Design Flow

    Generate Output Files Build Application Generate Bit Stream Configure FPGA Export Hardware Launch or Run on Hardware Figure 3-1. Bare-Metal Design Flow SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 4: Background

    ‘user clock’ in most FPGA EVMs. All other clock frequencies are derived internally through a clocking wizard. AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 5: Afe Spi Ip Container Pinout

    UART Terminal RX for debug diff_clock_rtl Input 100-Mhz differential clocking Reset_rtl Reset (Active High) typically connected to FPGA board Input reset SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 6: Ti Afe Spi Ip Container

    2. Click the + icon to add the location of TI provided IP (see Figure 6-2). Figure 6-2. Adding IP Repository AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 7: Create Block Designs With Ti Afe Spi Ip

    7-3). The header appears only if the inclusion of the IP repository is done correctly, as explained in previous steps. SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 8 6. The AFE SPI IP shows up in the block design (see Figure 7-5) if the previous steps were followed correctly. AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 9 The block design must then be validated for any errors and output products to generate. To validate the block diagram, right-click the block design under the Design Sources header. SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 10 FPGA pins, and the correct IO levels. The above steps complete the hardware design using TI AFE SPI IP. AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 11: Create New Platforms In Vitis

    Figure 8-1. New Platform Project 2. Enter the desired platform name. The name ZCU102ps was used as an example (see Figure 8-2). SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 12 Figure 8-3. Hardware Specification 4. Browse and select the .XSA file from the FPGA folder shared along with this document (see Figure 8-4). AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 13 5. Right-click the new platform project to open the drop-down menu. Click Build Project to start the build (see Figure 8-5). This can take some time to complete the build. Figure 8-5. Building the New Project SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 14: Create New Application Projects In Vitis

    9-2), click Next. Figure 9-2. New Application Project 3. Select the newly created platform ZCU102ps and click Next (see Figure 9-3). AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 15 Create New Application Projects in Vitis Figure 9-3. Selecting the Application Project 4. Type a new application name. ZCU102ps_SPI was used as an example. SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 16 Figure 9-5. Application Project Name 6. Select Hello World from the list of templates and click Finish (see Figure 9-6). AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 17 Create New Application Projects in Vitis Figure 9-6. Selecting Template 7. A fresh C project appears on top where the actual application development can start. SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 18: Build Application Projects

    1. Right-click the application name and select Build Project (see Figure 10-1). Figure 10-1. Building Project 2. Ensure that the project builds without any errors. AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 19: Configure The Axi Gpio

    For Example: XGpio_DiscreteWrite(&GPOs, 1, 0x14); This command sets JESD RSTn and RSTn to 1, sets all other bits to 0 SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 20: Configure The Axi Spi

    If D23 is set to 1, then it is a read operation and RdBufdev[2] stores the read back address contents • If D23 is set to 0, then it is a write operation and RdBufdev[2] has no significance AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 21: Create Boot Images To Run On Sd Card

    3. After reviewing the locations of the boot elf file, FPGA bit file, and application elf, click Create Image (see Figure 13-3). SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 22 Figure 13-4. SW6 Switch Positions 6. With the above setting on SW6 and SD card inserted, ZCU102 can now directly boot with the application. AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 23: Set Up And Power On Hardware

    5. After all the above connections are made, power up the setup. Note that the AFE EVM in this example is completely powered by the ZCU102 FMC interface. SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 24: Set Up Zcu102 Board Interface For Vadj_Fmc

    Figure 15-2. Setting VADJ 4. Confirm the same by reading the VADJ_FMC voltage. The voltage value must be 1.80 V (see Figure 15-3). AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 25 Set up ZCU102 Board Interface for VADJ_FMC Figure 15-3. VADJ_FMC Voltage SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 26: Debug Application Projects And Set Up Vitis Serial Terminal

    16-2) with baudrate 115200 (this can be used to see SPI write or read status). Figure 16-2. Vitis Serial Terminal AFE79xx SPI Bringup Guide With Xilinx FPGAs SBAU412 – NOVEMBER 2022 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...

  • Page 27: Execute The Application

    1. Click the right arrow button as shown in Figure 17-1. Figure 17-1. Executing Application 2. Notice the SPI logs being printed on the UART terminal. SBAU412 – NOVEMBER 2022 AFE79xx SPI Bringup Guide With Xilinx FPGAs Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated...
  • Page 28 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2022, Texas Instruments Incorporated...

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