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MSPM0G3507-Q1, MSPM0G3506-Q1, MSPM0G3505-Q1
SLASF88 – OCTOBER 2023
8 Detailed Description
The following sections describe all of the components that make up the devices in this data sheet. The
peripherals integrated into these devices are configured by software through Memory Mapped Registers
(MMRs). For more details, see the corresponding chapter of the
Technical Reference
Manual.
8.1 CPU
The CPU sub system (MCPUSS) implements an Arm Cortex-M0+ CPU, an instruction pre-fetch/cache, a system
timer, a memory protection unit, and interrupt management features. The Arm Cortex-M0+ is a cost-optimized,
32-bit CPU which delivers high performance and low power to embedded applications. Key features of the CPU
Sub System include:
•
Arm Cortex-M0+ CPU supporting clock frequencies from 32kHz to 80 MHz
– Armv6-M Thumb instruction set (little endian) with single-cycle 32x32 multiply instruction
– Single-cycle access to GPIO registers via Arm single-cycle IO port
•
Pre-fetch logic to improve sequential code execution, and I-cache with 4 64-bit cache lines
•
System timer (SysTick) with 24-bit down counter and automatic reload
•
Memory protection unit (MPU) with 8 programmable regions
•
Nested vectored interrupt controller (NVIC) with 4 programmable priority levels and tail-chaining
•
Interrupt groups for expanding the total interrupt sources, with jump index for low interrupt latency
8.2 Operating Modes
MSPM0G MCUs provide five main operating modes (power modes) to allow for optimization of the device power
consumption based on application requirements. In order of decreasing power, the modes are: RUN, SLEEP,
STOP, STANDBY, and SHUTDOWN. The CPU is active executing code in RUN mode. Peripheral interrupt
events can wake the device from SLEEP, STOP, or STANDBY mode to the RUN mode. SHUTDOWN mode
completely disables the internal core regulator to minimize power consumption, and wake is only possible via
NRST, SWD, or a logic level match on certain IOs. RUN, SLEEP, STOP, and STANDBY modes also include
several configurable policy options (for example, RUN.x) for balancing performance with power consumption.
To further balance performance and power consumption, MSPM0G devices implement two power domains: PD1
(for the CPU, memories, and high performance peripherals), and PD0 (for low speed, low power peripherals).
PD1 is always powered in RUN and SLEEP modes, but is disabled in all other modes. PD0 is always powered in
RUN, SLEEP, STOP, and STANDBY modes. PD1 and PD0 are both disabled in SHUTDOWN mode.
8.2.1 Functionality by Operating Mode (MSPM0G350x)
Supported functionality in each operating mode is given in
Functional key:
•
EN: The function is enabled in the specified mode.
•
DIS: The function is disabled (either clock or power gated) in the specified mode, but the function's
configuration is retained.
•
OPT: The function is optional in the specified mode, and remains enabled if configured to be enabled.
•
NS: The function is not automatically disabled in the specified mode, but it is not supported.
•
OFF: The function is fully powered off in the specified mode, and no configuration information is retained.
When waking up from an OFF state, all module registers must be re-configured to the desired settings by
application software.
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Product Folder Links:
MSPM0G3507-Q1 MSPM0G3506-Q1 MSPM0G3505-Q1
MSPM0 G-Series 80-MHz Microcontrollers
Table
8-1.
Copyright © 2023 Texas Instruments Incorporated
www.ti.com
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