Texas Instruments MSPM0G110 Series Advance Information

Texas Instruments MSPM0G110 Series Advance Information

Mixed-signal microcontrollers

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1 Features

Core
– Arm
®
32-bit Cortex
®
protection unit, frequency up to 80 MHz
Operating characteristics
– Extended temperature: –40°C up to 105°C
– Wide supply voltage range: 1.62 V to 3.6 V
Memories
– Up to 128KB of flash memory with built-in error
correction code (ECC)
– Up to 32KB of ECC protected SRAM with
hardware parity
High-performance analog peripherals
– Two simultaneous sampling 12-bit 4-Msps
analog-to-digital converters (ADC's) with up to
17 external channels
14-bit effective resolution at 250-ksps with
hardware averaging
– One general-purpose amplifier (GPAMP)
– Configurable 1.4-V or 2.5-V internal shared
voltage reference (VREF)
– Integrated temperature sensor
Optimized low-power modes
– RUN: 96 µA/MHz (CoreMark)
– SLEEP: 458 µA at 4 MHz
– STOP: 47 µA at 32 kHz
– STANDBY: 1.5 µA with RTC and SRAM
retention
– SHUTDOWN: 78 nA with IO wakeup capability
Intelligent digital peripherals
– 7-channel DMA controller
– Two 16-bit advanced control timers supporting
dead band insertion and fault handling
– Seven timers supporting up to 22 PWM
channels
One 16-bit general purpose timer
One 16-bit general purpose timer supports
QEI
Two 16-bit general-purpose timers support
low-power operation in STANDBY mode
One 32-bit general-purpose timer
Two 16-bit advanced timers with deadband
– Two window-watchdog timers
– RTC with alarm and calendar mode
Enhanced communication interfaces
– Four UART interfaces; one supports LIN,
IrDA, DALI, Smart Card, Manchester, and
three support low-power operation in STANDBY
mode
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change
without notice.
MSPM0G110x Mixed-Signal Microcontrollers
-M0+ CPU with memory
SLASF11A – FEBRUARY 2023 – REVISED JUNE 2023
2
– Two I
C interfaces supporting up to FM+
(1 Mbit/s), SMBus/PMBus, and wakeup from
STOP mode
– Two SPI interfaces, with one SPI interface
supporting upto 32Mbits/s
Clock system
– Internal 4- to 32-MHz oscillator with upto ±1.2%
accuracy (SYSOSC)
– Phase-locked loop (PLL) up to 80 MHz
– Internal 32-kHz oscillator (LFOSC)
– External 4- to 48-MHz crystal oscillator (HFXT)
– External 32-kHz crystal oscillator(LFXT)
– External clock input
Data integrity and encryption
– Cyclic redundancy checker (CRC-16, CRC-32)
Flexible I/O features
– Up to 60 GPIOs
Two 5-V tolerant IOs
Two high-drive IOs with 20-mA drive
strength
Development support
– 2-pin serial wire debug (SWD)
Package options
– 64-pin LQFP
– 48-pin LQFP , VQFN
– 32-pin VQFN
– 28-pin VSSOP
– 24-pin VQFN
Family members (also see
– MSPM0G1105: 32KB flash, 16KB RAM
– MSPM0G1106: 64KB flash, 32KB RAM
– MSPM0G1107: 128KB flash, 32KB RAM
Development kits and software (also see
and
Software)
LP-MSPM0G3507 LaunchPad
kit
– MSP Software Development Kit (SDK)

2 Applications

Motor control
Home appliances
Uninterruptible power supplies and inverters
Electronic point of sale systems
Medical and healthcare
Test and measurement
Factory automation and control
Industrial transport
Grid infrastructure
Smart metering
Communication modules
Lighting
MSPM0G1107, MSPM0G1106
Device
Comparison)
Tools
development

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Summary of Contents for Texas Instruments MSPM0G110 Series

  • Page 1: Features

    MSPM0G1107, MSPM0G1106 SLASF11A – FEBRUARY 2023 – REVISED JUNE 2023 MSPM0G110x Mixed-Signal Microcontrollers – Two I C interfaces supporting up to FM+ 1 Features (1 Mbit/s), SMBus/PMBus, and wakeup from • Core STOP mode – Two SPI interfaces, with one SPI interface –...
  • Page 2: Description

    See MSP430™ System-Level ESD Considerations for more information. The principles in this application note are applicable to MSPM0 MCUs. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 3: Functional Block Diagram

    PD1, CPU ACCESS ONLY HFXIN, HFXOUT VCORE, NRST PD1, CPU/DMA ACCESS ROSC PD1/PD0, CPU/DMA ACCESS CLK_OUT, FCC_IN PD0, CPU/DMA ACCESS Figure 4-1. MSPM0G110x Functional Block Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 4: Table Of Contents

    Caution......71 8.2 Operating Modes............10.8 Glossary..............71 8.3 Power Management Unit (PMU)....... 11 Mechanical, Packaging, and Orderable 8.4 Clock Module (CKM)..........52 Information..............8.5 DMA................12 Revision History............Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 5: Device Comparison

    The package size (length × width) is a nominal value and includes pins, where applicable. For the package dimensions with tolerances, see Section For more infromation about the device name, see Section 10.2. Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 6: Pin Configuration And Functions

    For full descriptions of the pin functions, see the Pin Attributes and Signal Descriptions sections. 6.1 Pin Diagrams Power Reset High-Speed I/O (HSIO) 5-V Tolerant Open-Drain I/O (ODIO) High-Drive I/O (HDIO) Figure 6-1. Pin Diagram Color Coding Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 7 PA19 / SWDIO PA30 PA20 / SWCLK PA29 PB17 / A1_4 PA28 PB18 / A1_5 PB19 / A1_6 PA0 / FCC_IN Figure 6-2. 64-Pin PM (LQFP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 8 PA12 / FCC_IN PA4 / LFCLK_IN / LFXOUT PB16 PA5 / HFXIN / FCC_IN PB15 PA6 / HFCLK_IN / HFXOUT Figure 6-3. 48-Pin PT (LQFP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 9 PA4 / LFCLK_IN / LFXOUT PA12 / FCC_IN PA5 / HFXIN / FCC_IN PB16 PA6 / HFCLK_IN / HFXOUT PB15 Thermal pad Figure 6-4. 48-Pin RGZ (VQFN) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 10 PA15 / A1_0 PA3 / LFXIN PA14 / CLK_OUT / A0_12 PA13 PA4 / LFCLK_IN / LFXOUT Thermal pad Figure 6-5. 32-Pin RHB (VQFN) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 11 PA4 / LFCLK_IN / LFXOUT PA15 / A1_0 PA14 / CLK_OUT / A0_12 PA11 PA10 / CLK_OUT PA9 / RTC_OUT / CLK_OUT Figure 6-6. 28-Pin DGS28 (VSSOP) (Top View) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 12 Thermal pad Figure 6-7. 24-Pin RGE (VQFN) (Top View) Note For full pin configuration and functions for each package option, refer to Pin Attributes Signal Descriptions. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 13: Pin Attributes

    Each digital I/O on a device is mapped to a specific Pin Control Management Register (PINCMx) which allows users to configure the desired Pin Function using the PINCM.PF control bits. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 14 UART1_RX [2] / UART3_RTS [3] / TIMA1_C1 [4] / Standard TIMA0_C2N [5] / TIMA1_C1N [6] UART1_TX [2] / SPI0_CS0 [3] / UART0_RTS [4] / 54 16 12 Standard TIMA0_C0 [5] / TIMA1_C0N [6] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 15 SWCLK [2] 13 35 24 23 16 Standard PB17 UART2_TX [2] / SPI0_PICO [3] / SPI1_CS1 [4] / A1_4 14 36 Standard TIMA1_C0 [5] / TIMA0_C2 [6] Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 16 Table 6-2. Digital IO Features by IO Type DRIVE INVERSION HYSTERESIS PULLUP PULLDOWN WAKEUP IO STRUCTURE STRENGTH CONTROL CONTROL RESISTOR RESISTOR LOGIC CONTROL Standard-drive Standard-drive with wake High-drive High-speed Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 17: Signal Descriptions

    Output of low-frequency crystal oscillator LFXT ROSC External resistor used for improving oscillator accuracy SWCLK Serial wire debug input clock Debug SWDIO Serial wire debug data input/output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 18 NAME 64 PM DGS2 VQFN FCC_IN Frequency clock counter input GPAMP_IN+ GPAMP non-inverting terminal input General- Purpose GPAMP_IN- GPAMP inverting terminal input Amplifier GPAMP_OUT GPAMP output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 19 – – – General-purpose digital I/O PA30 – – – – General-purpose digital I/O General-purpose digital I/O with wake up from PA31 – – – SHUTDOWN Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 20 General-purpose digital I/O PB27 – – – – General-purpose digital I/O I2C0_SCL I2C0 serial clock I2C0_SDA I2C0 serial data I2C1_SCL I2C1 serial clock I2C1_SDA I2C1 serial data Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 21 Power VCORE Regulated core power supply output QFN package exposed thermal pad. TI recommends QFN Pad – – – connection to V RTC_OUT RTC clock output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 22 SPI1 clock signal input – SPI peripheral mode SPI1_SCK Clock signal output – SPI controller mode SPI1_POCI – SPI1 controller in/peripheral out SPI1_PICO SPI1 controller out/peripheral in System NRST Reset input active low Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 23 General purpose timer 7 CCR1 capture input/ compare TIMG7_C0 output General purpose timer 7 CCR1 capture input/ compare TIMG7_C1 output General purpose timer 8 CCR0 capture input/ compare TIMG8_C0 output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 24 Advanced control timer 0 CCR0 capture input/compare TIMA0_C0N output (inverting) Advanced control timer 0 CCR1 capture input/ TIMA0_C1 compare output Advanced control timer 0 CCR1 capture input/ TIMA0_C1N compare output (inverting) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 25 Advanced control timer 1 CCR0 capture input/ TIMA1_C0 compare output Advanced control timer 0 CCR3 capture input/ TIMA1_C0N – compare output (inverting) Advanced control timer 1 CCR1 capture input/ TIMA1_C1 compare output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 26 TIMA_FAL0 Advanced control timer 0 fault handling input Timer (continued) TIMA_FAL1 Advanced control timer 1 fault handling input TIMA_FAL2 Advanced control timer 2 fault handling input Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 27 UART2_TX UART2 transmit data UART2_RX UART2 receive data UART2_CTS – UART2 "clear to send" flow control input UART2_RTS – UART2 "request to send" flow control output Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 28 When using VREF+ and VREF- to bring in an external voltage reference for analog peripherals such as the ADC, a decoupling capacitor must be placed on VREF+ to VREF-/GND with a capacitance based on the external reference source Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 29: Connections For Unused Pins

    Section 9.1 Any unused pin with a function that is shared with general-purpose I/O should follow the "PAx and PBx" unused pin connection guidelines. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 30: Specifications

    MCLK, CPUCLK frequency with 2 flash wait states MCLK, CPUCLK frequency with 1 flash wait state MCLK (PD1 bus clock) MCLK, CPUCLK frequency with 0 flash wait states Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 31: Thermal Information

    θJC(top) Junction-to-board thermal resistance 41.3 °C/W θJB VSSOP-28 (DGS28) Ψ Junction-to-top characterization parameter °C/W Ψ Junction-to-board characterization parameter 41.0 °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 32 °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 33: Supply Current Characteristics

    ULPCLK=LFCLK STANDBY Mode LFCLK=LFXT, STOPCLKSTBY=0, 6.91 STBY0 RTC enabled LFCLK=LFOSC, STOPCLKSTBY=1, 15.5 RTC enabled 32kHz LFCLK=LFXT, STOPCLKSTBY=1, 15.5 STBY1 RTC enabled LFCLK=LFXT, STOPCLKSTBY=1, 15.6 GPIOA enabled Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 34: Power Supply Sequencing

    Device operating in RUN, SLEEP, or STOP mode. 7.6.2 Power Supply Ramp Figure 7-1 gives the relationship of POR- POR+, BOR0-, and BOR0+ during power-up and power-down. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 35: Flash Memory Characteristics

    Program time is defined as the time from when the program command is triggered until the command completion interrupt flag is set in the flash controller. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 36: Timing Characteristics

    The wake-up time is measured from the edge of an external wake-up signal (IOMUX wake-up event) to the time that first instruction of the user program is executed. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 37: Clock Specifications

    , after which the target accuracy is SYSOSC settle,SYSOSC settle,SYSOSC achieved. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 38 The LFCLK monitor may be used to monitor the LFXT or LFCLK_IN. It will always fault below the MIN fault frequency, and will never fault above the MAX fault frequency. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 39: Digital Io

    Hysteresis All I/O except 0.1*VDD ODIO (2) (3) High-Z leakage current SDIO All I/O except Pull up resistance kΩ ODIO Pull down resistance kΩ Input capacitance Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 40 -40 °C ≤T ≤130 °C VDD≥2.7V, DRV=1, |I =20mA ,max VDD-0.4 VDD≥1.71V, DRV=1, |I =10mA ,max HDIO VDD≥2.7V, DRV=0, |I =6mA ,max VDD-0.4 VDD≥1.71V, DRV=0, |I =2mA ,max Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 41 VDD ≥ 2.7V, DRV = 0, CL= 20pF ODIO VDD ≥ 1.71V, FM , CL= 20pF - 100pF All output ports Output rise/fall time VDD ≥ 1.71V 0.3*f except ODIO Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 42: Analog Mux Vboost

    R– All external reference specifications are measured with V = VREF+ = VDD = 3.3V and V = VREF- = VSS = 0V Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 43 Use the following equations to solve for the minimum sampling time (T) required for an ADC conversion: 1. Tau = (R )* C 2. K= ln(2 /Settling error) – ln((C Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 44: Temperature Sensor

    A ceramic capacitor with package size of 0805 or smaller is preferred. Up to ±20% tolerance is acceptable The VREF module should only be enabled when C is connected and should not be enabled otherwise. VREF Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 45: Gpamp

    GPAMP disable time disable Cycles = 200 pF, Vstep = 0.3V to VDD - GPAMP settling time Noninverting, unity gain µs SETTLE 0.3V, 0.1%, ENABLE = 0x1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 46: I2C

    (unless otherwise noted) PARAMETERS TEST CONDITIONS UNIT Clock max speed = 32MHz SPI clock frequency 1.62 < VDD < 3.6V Controller mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 47 Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge Specifies how long data on the output is valid after the output changing SCLK clock edge Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 48: Uart

    UART in Power Domain0 UART BITCLK clock frequency(equals UART in Power Domain1 BITCLK baud rate in MBaud) BITCLK clock frequency(equals UART in Power Domain0 BITCLK baud rate in MBaud) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 49: Timx

    TIMx in Power Domain 0, f = 40MHz TIMxCLK TIMxCLK 7.20 Emulation and Debug 7.20.1 SWD Timing over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT SWD frequency Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 50: Detailed Description

    OFF: The function is fully powered off in the specified mode, and no configuration information is retained. When waking up from an OFF state, all module registers must be re-configured to the desired settings by application software. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 51 SPI0, SPI1 Peripherals TIMA0, TIMA1 TIMG6, TIMG7 TIMG12 TIMG0, TIMG8 UART0, UART1, UART2 Peripherals I2C0, I2C1 GPIOA, GPIOB WWDT0, WWDT1 ADC0, ADC1 NS (triggers supported) Analog GPAMP Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 52: Power Management Unit (Pmu)

    HFCLK: High frequency clock derived from HFXT or HFCLK_IN, available in RUN and SLEEP mode • HSCLK: High speed clock derived from HFCLK or the SYSPLL, available in RUN and SLEEP mode Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 53: Dma

    • Peripheral event transferred to the DMA as a DMA trigger (DMA Event) – Example: UART data receive trigger to DMA to request a DMA transfer Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 54: Memory

    0x201F.FFFF 0x201F.FFFF 0x201F.FFFF SRAM (SRAM) 0x2020.0000 to 0x2020.0000 to 0x2020.0000 to Un-checked 0x202F.FFFF 0x202F.FFFF 0x202F.FFFF ECC/parity 0x2030.0000 to 0x2030.0000 to 0x2030.0000 to 0x203F.FFFF 0x203F.FFFF 0x203F.FFFF code Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 55 0x400C7000 0x2000 EVENT 0x400C9000 0x3000 NVMNW 0x400CD000 0x2000 I2C0 0x400F0000 0x2000 I2C1 0x400F2000 0x2000 UART1 0x40100000 0x2000 UART2 0x40102000 0x2000 UART0 0x40108000 0x2000 MCPUSS 0x40400000 0x2000 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 56 ADC1 0x40558000 0x1000 TIMA0 0x40860000 0x2000 TIMA1 0x40862000 0x2000 TIMG6 0x40868000 0x2000 TIMG7 0x4086A000 0x2000 TIMG12 0x40870000 0x2000 Aliased region of ADC0 and ADC1 memory-mapped registers Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 57: Flash Memory

    CPU frequency range of the device. MSPM0Gxx MCUs also provides up to 32KB of ECC protected SRAM with hardware parity. SRAM memory may be used for storing volatile information such as the call stack, Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 58: Gpio

    Operates in RUN, SLEEP, and STOP modes Table 8-7. ADC Channel Mapping (1) (2) SIGNAL NAME SIGNAL NAME CHANNEL[0:7] CHANNEL[8:15] ADC0 ADC1 ADC0 ADC1 A0_0 A1_0 A1_7 A0_7 A0_1 A1_1 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 59: Temperature Sensor

    The GPAMP supports the following features: • Software selectable chopper stabilization • Rail-to-rail input and output • Programmable internal unity gain feedback loop Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 60: Crc

    Support Standard-mode (Sm), with a bit rate up to 100 kbit/s • Support Fast-mode (Fm), with a bit rate up to 400 kbit/s • Support Fast-mode Plus (Fm+), with a bit rate up to 1 Mbit/s Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 61: Spi

    RTC clock output to pin for calibration Only SPI signals on HSIO pins support data rate > 16 Mbits/s; see the Pin Diagrams section for HSIO pins. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 62: Timers (Timx)

    8-bit – – – – – – TIMG12 32-bit – – – – – – – TIMA0 16-bit 8-bit 8-bit – TIMA1 16-bit 8-bit 8-bit – Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 63 Event Subscriber Port 0 Event Subscriber Port 1 18-31 Reserved For more details, see the TIMx chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 64: Device Analog Connections

    GPAMP Output Supply/Battery Monitor A1_0:A1_7 A0_7 Temp Sense ADC1 GPAMP Output Supply/Battery Monitor GPAMP Internal signal to ADC0, ADC1, GPAMP_IN+ GPAMP GPAMP_OUT GPAMP_IN- Figure 8-1. Analog Connections Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 65: Input/Output Diagrams

    Peripheral 01 DOUT Peripheral 15 RSTN Driver Logic Unassigned Peripheral 01 Hi-Z Peripheral 15 RSTN PF != 0 PIPU PIPD SHUTDOWN RELEASE Figure 8-2. Superset Input/Output Diagram Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 66: Serial Wire Debug Interface

    Refer to Factory Constants chapter of the MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual. Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 67: Identification

    The device revision and identification information are also included as part of the top-side marking on the device package. The device-specific errata sheet describes these markings (see Section 10.4) Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 68: Applications, Implementation, And Layout

    Debug tool are optional, but SWCLK NRST must be Debug interface pulled high to VDD for the device to start. Figure 9-1. Basic Application Schematic Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 69: Device And Documentation Support

    10.1 Getting Started and Next Steps For more information on the MSP low-power microcontrollers and the tools and libraries that are available to help with development, visit the Texas Instruments Arm Cortex-M0+ MCUs page.
  • Page 70: Tools And Software

    TI Arm Clang is included in Code Composer Studio. GNU Arm Embedded The MSPM0 SDK supports development using the open-source Arm GNU Toolchain Toolchain.Arm GCC is supported by Code Composer Studio (CCS). Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
  • Page 71: Documentation Support

    All trademarks are the property of their respective owners. 10.7 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 72: Mechanical, Packaging, And Orderable Information

    12 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES June 2023 Initial Public Release Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: MSPM0G1107 MSPM0G1106...
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