Interrupt Request Bit; Interrupt Enable Flag; Interrupt Priority Level - Renesas M16C Series User Manual

M30240 Group

4.1.3.1 Interrupt Request Bit

The interrupt request bit is located in the interrupt control register of each interrupt. It is set to "1" by
hardware when an interrupt is requested. After the interrupt is accepted and jumps to the correspond-
ing interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set
to "0" by software. (Do not set this bit to "1").

4.1.3.2 Interrupt Enable Flag

The interrupt enable flag (I flag) is located in the flag register (FLG). A non-maskable interrupt can be
enabled or disabled using the interrupt enable flag (I flag). Setting this flag to "1" enables all maskable
interrupts; Setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset. Figure 4.3
shows the timing change in the I flag to the interrupt.
When the content of the I flag is changed, the acceptance of an interrupt request occurs in the follow-
ing timing:
• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes effect as
the REIT instruction is executed.
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the accep-
tance of the interrupt is effective as the next instruction is executed.
When changed by REIT instruction
Interrupt request generated
(If I flag is changed from 0 to 1 by REIT instruction)
When changed by FCLR, FSET, POPC, or LDC instruction
Interrupt request generated
instruction
(If I flag is changed from 0 to 1 by FSET instruction)
Figure 4.3: Timing reflecting the change in the I flag to the interrupt

4.1.3.3 Interrupt Priority Level

A non-maskable interrupt can be enabled or disabled using the interrupt priority level selection bit, and
processor interrupt priority level (IPL).
The interrupt priority level selection bit is located in the interrupt control register of each interrupt. The
IPL is located in the flag register (FLG). When an interrupt request occurs, the interrupt priority level
is compared to the IPL. Use the interrupt priority level select bit to set the interrupt priority level. The
interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting
the interrupt priority level to "0" disables the interrupt.
Table 4.4 shows the settings of interrupt priority levels and Table 4.5 shows the interrupt levels en-
abled, according to the contents of the IPL. Note: The interrupt enable flag (I flag), interrupt request
bit, interrupt priority select bit, and IPL are independent of each other.
Rev.1.00 Sep 24, 2003 Page 336 of 360
Determination whether or not to
accept interrupt request
Previous
REIT
instruction
Previous
FSET I
Time
Interrupt sequence
Determination whether or not to
accept interrupt request
Next instruction Interrupt sequence
Overview of Interrupts
Time