Figure 15.18 Sample Flowchart For Master Receive Mode - Renesas H8/36912 Series User Manual

16-bit single-chip microcomputer
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Mater receive mode
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
Dummy-read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Last receive
- 1?
Read ICDRR
Set ACKBT in ICIER to 1
Set RCVD in ICCR1 to 1
Read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Clear STOP in ICSR.
Write 0 to BBSY
and SCP
Read STOP in ICSR
No
STOP=1 ?
Read ICDRR
Clear RCVD in ICCR1 to 0
Clear MST in ICCR1 to 0
End
Rev. 1.00, 11/03, page 250 of 376
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[1] Clear TEND, select master receive mode, and then clear TDRE.*
[2] Set acknowledge to the transmit device.*
[1]
[3] Dummy-read ICDDR.*
[4] Wait for 1 byte to be received
[2]
[5] Check whether it is the (last receive - 1).
[3]
[6] Read the receive data last.
[7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[4]
[8] Read the (final byte - 1) of receive data.
Yes
Yes
[9] Wait for the last byte to be receive.
[5]
No
[10] Clear the STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[7]
[13] Read the last byte of receive data.
[14] Clear RCVD.
[8]
[15] Set slave receive mode.
[9]
Yes
[10]
[11]
[12]
Yes
[13]
[14]
[15]
Note: Do not activate an interrupt during the execution of steps [1] to [3].
When one byte is received, steps [2] to [6] are skipped after step [1],
before jumping to step [7]. The step [8] is dammy-read in ICDRR.

Figure 15.18 Sample Flowchart for Master Receive Mode

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