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(f) Page ROM access timing
TASW
BUSCLK (output)
< t
CSZ0-CSZ7
(output)
< t
A0-A25 (output)
< t
DKWRH
WRZ0-WRZ3,
WRSTBZ
(output)
< t
DKRDH
RDZ (output)
D0-D31
(I/O)
WAITZ (input)
< t
DKBSL
BCYSTZ (output)
Remarks 1. Timing when the number of waits inserted by the DWC0 or DWC1 register is 0, the number
of idle states inserted by the BCC register is 1, and the number of waits inserted by the ASC
register is 1.
2.
Broken lines indicate high impedance.
CHAPTER 1 PRODUCT SPECIFCATIONS
Figure 1-8. Page ROM Access Timing
T1
TDW
TW
>
DKA
>
DKA
>
>
< t
>
DKRDL
< t
>
HKW
< t
>
SKW
>
< t
>
DKBSH
User's Manual A19069EJ2V0UM
T2
TO1
TPRW
< t
>
DKA
< t
>
HKID
< t
>
SKID
< t
>
< t
>
HKW
HKW
< t
>
< t
>
SKW
SKW
TW
TO2
< t
>
DKA
< t
>
DKA
< t
>
D KRDH
< t
>
HKID
< t
>
SKID
< t
>
HKW
< t
>
SKW
25
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