Bits 12-14: Processor Interrupt Priority Level (Ipl); Bit 15: Reserved Area - Renesas R8C/Tiny Series Software Manual

Chapter 1 Overview

1.4.10 Bits 12-14: Processor interrupt priority level (IPL)

The processor interrupt priority level (IPL) consists of three bits, allowing you to specify eight processor
interrupt priority levels from level 0 to level 7. If a requested interrupt's priority level is higher than the
processor interrupt priority level (IPL), this interrupt is enabled.

1.4.11 Bit 15: Reserved area

b15
IPL
Figure 1.4.1 Configuration of flag register (FLG)
U I O B S Z
7
1.4 Flag Register (FLG)
b0
Flag register (FLG)
D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area