Motorola MPC860 PowerQUICC User Manual page 94

Part I. Overview
Table 2-1. MPC860 Internal Memory Map (Continued)
Offset
99A TCR2ÑTimer 2 capture register
99C TCN1ÑTimer 1 counter
99E TCN2ÑTimer 2 counter
9A0 TMR3ÑTimer 3 mode register
9A2 TMR4ÑTimer 4 mode register
9A4 TRR3ÑTimer 3 reference register
9A6 TRR4ÑTimer 4 reference register
9A8 TCR3ÑTimer 3 capture register
9AA TCR4ÑTimer 4 capture register
9AC TCN3ÑTimer 3 counter
9AE TCN4ÑTimer 4 counter
9B0 TER1ÑTimer 1 event register
9B2 TER2ÑTimer 2 event register
9B4 TER3ÑTimer 3 event register
9B6 TER4ÑTimer 4 event register
9B8Ð9BF Reserved
9C0 CPCRÑCP command register
9C2Ð9C3 Reserved
9C4 RCCRÑRISC controller conÞguration register
9C6Ð9C8 Reserved
9CC RCTR1ÑRISC controller trap register 1
9CE RCTR2ÑRISC controller trap register 2
9D0 RCTR3ÑRISC controller trap register 3
9D2 RCTR4ÑRISC controller trap register 4
9D4Ð9D5 Reserved
9D6 RTERÑRISC timer event register
9D8Ð9D9 Reserved
9DA RTMRÑRISC timers mask register
9DCÐ9EF Reserved
9F0 BRGC1ÑBRG1 conÞguration register
9F4 BRGC2ÑBRG2 conÞguration register
9F8Ð9FF Reserved
A00 GSMR_L1ÑSCC1 general mode register
A04 GSMR_H1ÑSCC1 general mode register
2-6
Name
Communications Processor (CP)
Baud Rate Generators
SCC1
MPC860 PowerQUICC UserÕs Manual
Size Section/Page
16 bits 18.2.3.4/18-10
16 bits 18.2.3.5/18-10
16 bits 18.2.3.5/18-10
16 bits 18.2.3.2/18-9
16 bits 18.2.3.2/18-9
16 bits 18.2.3.3/18-10
16 bits 18.2.3.3/18-10
16 bits 18.2.3.4/18-10
16 bits 18.2.3.4/18-10
16 bits 18.2.3.5/18-10
16 bits 18.2.3.5/18-10
16 bits 18.2.3.6/18-11
16 bits 18.2.3.6/18-11
16 bits 18.2.3.6/18-11
16 bits 18.2.3.6/18-11
8 bytes Ñ
16 bits 19.5.2/19-6
2 bytes Ñ
16 bits 19.5.1/19-4
3 bytes Ñ
16 bits Used only by optional RAM microcode
16 bits Used only by optional RAM microcode
16 bits Used only by optional RAM microcode
16 bits Used only by optional RAM microcode
2 bytes Ñ
16 bits 19.7.4/19-15
2 bytes Ñ
16 bits 19.7.4/19-15
20 bytes Ñ
32 bits 21.4.1/21-40
32 bits 21.4.1/21-40
8 bytes Ñ
32 bits 22.1.1/22-3
32 bits 22.1.1/22-3
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