Communications Processor Module (Cpm) - Motorola MPC860 PowerQUICC User Manual

Part I. Overview
than the time base decrementer, PLL, memory controller, RTC, and then places the CPM
in low-power standby mode. Sleep mode disables everything except the RTC and PIT,
leaving the PLL active for quick wake-up. Deep sleep mode disables the PLL for lower
power but slower wake-up. Low-power stop disables all logic in the processor except the
minimum logic required to restart the device, providing the lowest power consumption but
requiring the longest wake-up time.

1.7 Communications Processor Module (CPM)

The MPC860 is the next generation MC68360 QUICC and like its predecessor implements
a dual-processor architecture. This dual-processor architecture provides both a
high-performance general purpose processor for application programming use as well as a
special purpose communication processor (CPM) uniquely designed for communications
needs.
The CPM contains features that allow the MPC860 to excel in communications and
networking products as did the MC68360 QUICC which preceded it. These features may
be divided into three sub-groups:
¥ Communications processor (CP)
¥ Sixteen independent DMA (SDMA) controllers
¥ Four general-purpose timers
The CP provides the communication features of the MPC860. Included are a RISC
processor, two serial communication controllers (SCC), four serial management controllers
(SMC), one serial peripheral interface (SPI), one I
an interrupt controller, a time-slot assigner, three parallel ports, a parallel interface port,
four independent baud rate generators, and sixteen serial DMA channels to support the
SCCs, SMCs, SPI, and I
The SDMAs provide two channels of general-purpose DMA capability for each
communications channel. They offer high-speed transfers, 32-bit data movement, buffer
chaining, and independent request and acknowledge logic.
The four general-purpose timers on the CPM are identical to the timers found on the
MC68360 and still support the internal cascading of two timers to form a 32-bit timer.
The MPC860 maintains the best features of the MC68360 QUICC, while making changes
required to provide for the increased ßexibility, integration, and performance requested by
customers demanding the performance of the PowerPC architecture. The addition of a
multiply-and-accumulate (MAC) function on the CPM further enhances the MPC860,
enabling various modem and DSP applications. Because the CPM architectural approach
remains intact between the MPC860 and the MC68360 QUICC, a user of the MC68360
QUICC can easily become familiar with the MPC860.
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C.
MPC860 PowerQUICC UserÕs Manual
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C interface, 5 Kbytes of dual-port RAM,
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