Architecture Overview - Motorola MPC860 PowerQUICC User Manual

¥ Debug interface
Ñ Eight comparators: four operate on instruction address, two operate on data
address, and two operate on data
Ñ Supports Conditions: = ¹ < >
Ñ Each watchpoint can generate a break point internally
¥ 3.3 V operation with 5-V TTL compatibility
¥ 357-pin ball grid array (BGA) package
Instruction
Bus
PowerPC
Processor
Core
Load/Store
Bus
Parallel I/O
4 Baud Rate
Generators
Parallel Interface
Port
SCC1

1.2 Architecture Overview

The MPC860 integrates an embedded PowerPC core with high-performance, low-power
peripherals to extend the Motorola Data Communications family of embedded processors
even farther into high-end communications and networking products.
The MPC860 is comprised of three modules that each use the 32-bit internal bus: the
PowerPC core, the system integration unit (SIU), and the communication processor module
(CPM). The MPC860 block diagram is shown in Figure 1-1.
MOTOROLA
4 K
Instruction Cache
Instruction MMU
32 Entry ITLB
4 K
Data Cache
Data MMU
32 Entry DTLB
4 Interrupt 5 K Dual-Port
Timers Controllers
32-Bit RISC Controller
and Program
ROM
Timers
SCC2 SCC3 SCC4
Serial Interface and Time-Slot Assigner (TSA)
Figure 1-1. MPC860 Block Diagram
Chapter 1. MPC860 Overview
System Interface Unit (SIU)
Memory Controller
UniÞed
Internal
Bus
Bus Interface
Unit
System Functions
Real-Time Clock
PCMCIA-ATA Interface
16 Virtual
1
RAM
Serial
and
2
Independent
DMA
MAC
Channels
SMC1 SMC2 SPI
Serial Interface
Part I. Overview
External
Bus Interface
Unit
2
I C
1-5