Motorola MPC860 PowerQUICC User Manual page 95

Table 2-1. MPC860 Internal Memory Map (Continued)
Offset
A08 PSMR1ÑSCC1 protocol speciÞc mode register
A0AÐA0B Reserved
A0C TODR1ÑSCC1 transmit-on-demand register
A0E DSR1ÑSCC1 data synchronization register
A10 SCCE1ÑSCC1 event register
A12ÐA13 Reserved
A14 SCCM1ÑSCC1 mask register
A16 Reserved
A17 SCCS1ÑSCC1 status register
A18ÐA1F Reserved
A20 GSMR_L2ÑSCC2 general mode register
A24 GSMR_H2ÑSCC2 general mode register
A28 PSMR2ÑSCC2 protocol-speciÞc mode register
A2A Reserved
A2C TODR2ÑSCC2 transmit on demand register
A2E DSR2ÑSCC2 data synchronization register
A30 SCCE2ÑSCC2 event register
A32 Reserved
A34 SCCM2ÑSCC2 mask register
A36 Reserved
MOTOROLA
Name
Serial Communication Controller 2 (SCC2)
Chapter 2. Memory Map
Size Section/Page
16 bits 22.1.2/22-10
23.16/23-13 (UART)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BiSYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
2 bytes Ñ
16 bits 22.1.4/22-10
16 bits 22.1.3/22-10
16 bits 23.19/23-19 (UART)
24.11/24-12 (HDLC)
2 bytes
26.13.1/26-9 (Asynchronous HDLC)
16 bits
27.14/27-15 (BiSYNC)
28.21/28-25 (Ethernet)
29.12/29-12 (Transparent)
1 byte Ñ
8 bits 23.20/23-21 (UART)
24.12/24-14 (HDLC)
26.13.2/26-10 (Asynchronous HDLC)
27.15/27-16 (BiSYNC)
29.13/29-13 (Transparent)
8 bytes Ñ
32 bits 22.1.1/22-3
32 bits 22.1.1/22-3
16 bits 22.1.2/22-10
23.16/23-13 (UART)
26.13.3/26-11 (Asynchronous HDLC)
27.11/27-10 (BISYNC)
28.18/28-19 (Ethernet)
29.9/29-8 (Transparent)
16 bits Ñ
16 bits 22.1.4/22-10
16 bits 22.1.3/22-10
16 bits 23.20/23-21 (UART)
24.11/24-12 (HDLC)
26.13.1/26-9 (Asynchronous HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
16 bits Ñ
16 bits 23.20/23-21 (UART)
24.12/24-14 (HDLC)
26.13.3/26-11 (Asynchronous HDLC)
27.15/27-16 (BISYNC)
29.13/29-13 (Transparent)
8 bits Ñ
Part I. Overview
2-7