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Manuals and User Guides for Texas Instruments OMAP-L1x. We have
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Texas Instruments OMAP-L1x manual available for free PDF download: User Manual
Texas Instruments OMAP-L1x User Manual (136 pages)
Processor Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module
Brand:
Texas Instruments
| Category:
Controller
| Size: 0.68 MB
Table of Contents
Table of Contents
3
Preface
10
Introduction
12
Purpose of the Peripheral
12
Features
12
Functional Block Diagram
13
EMAC and MDIO Block Diagram
13
Industry Standard(S) Compliance Statement
14
Architecture
14
Clock Control
14
Memory Map
14
Signal Descriptions
14
Ethernet Configuration-MII Connections
15
EMAC and MDIO Signals for MII Interface
15
Ethernet Configuration-RMII Connections
16
EMAC and MDIO Signals for RMII Interface
16
Ethernet Protocol Overview
17
Ethernet Frame Format
17
Ethernet Frame Description
17
Programming Interface
18
Basic Descriptor Format
18
Typical Descriptor Linked List
19
Basic Descriptor Description
19
Transmit Buffer Descriptor Format
22
Receive Buffer Descriptor Format
25
EMAC Control Module
29
EMAC Control Module Block Diagram
29
MDIO Module
30
MDIO Module Block Diagram
31
EMAC Module
35
EMAC Module Block Diagram
35
MAC Interface
37
2.10 Packet Receive Operation
41
Receive Frame Treatment Summary
44
Middle of Frame Overrun Treatment
45
2.11 Packet Transmit Operation
46
2.12 Receive and Transmit Latency
47
2.13 Transfer Node Priority
47
2.14 Reset Considerations
48
2.15 Initialization
49
2.16 Interrupt Support
51
2.17 Power Management
55
2.18 Emulation Considerations
55
Emulation Control
55
EMAC Control Module Registers
56
EMAC Control Module Revision ID Register (REVID)
57
EMAC Control Module Revision ID Register (REVID) Field Descriptions
57
EMAC Control Module Software Reset Register (SOFTRESET)
58
EMAC Control Module Interrupt Control Register (INTCONTROL)
59
EMAC Control Module Interrupt Core Receive Threshold Interrupt Enable Registers (C0RXTHRESHEN-C2RXTHRESHEN)
60
EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (Cnrxthreshen)
60
EMAC Control Module Interrupt Core Receive Interrupt Enable Registers (C0RXEN-C2RXEN)
61
EMAC Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (Cnrxen)
61
EMAC Control Module Interrupt Core Transmit Interrupt Enable Registers (C0TXEN-C2TXEN)
62
EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (Cntxen)
62
EMAC Control Module Interrupt Core Miscellaneous Interrupt Enable Registers (C0MISCEN-C2MISCEN)
63
EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (Cnmiscen)
63
EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers (C0RXTHRESHSTAT-C2RXTHRESHSTAT)
64
EMAC Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (Cnrxthreshstat)
64
EMAC Control Module Interrupt Core Receive Interrupt Status Registers (C0RXSTAT-C2RXSTAT)
65
EMAC Control Module Interrupt Core 0-2 Receive Interrupt Status Register (Cnrxstat)
65
EMAC Control Module Interrupt Core Transmit Interrupt Status Registers (C0TXSTAT-C2TXSTAT)
66
EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (Cntxstat)
66
EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers (C0MISCSTAT-C2MISCSTAT)
67
EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (Cnmiscstat)
67
3.12 EMAC Control Module Interrupt Core Receive Interrupts Per Millisecond Registers
68
(C0Rximax-C2Rximax)
68
EMAC Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (Cnrximax)
68
EMAC Control Module Interrupt Core Transmit Interrupts Per Millisecond Registers (C0TXIMAX-C2TXIMAX)
69
EMAC Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (Cntximax)
69
MDIO Registers
70
MDIO Revision ID Register (REVID)
70
Management Data Input/Output (MDIO) Registers
70
MDIO Revision ID Register (REVID) Field Descriptions
70
MDIO Control Register (CONTROL)
71
MDIO Control Register (CONTROL) Field Descriptions
71
PHY Acknowledge Status Register (ALIVE)
72
PHY Link Status Register (LINK)
72
PHY Acknowledge Status Register (ALIVE) Field Descriptions
72
PHY Link Status Register (LINK) Field Descriptions
72
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW)
73
MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions
73
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED)
74
MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions
74
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
75
MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions
75
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)
76
MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions
76
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
77
MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions
77
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
78
MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field Descriptions
78
MDIO User Access Register 0 (USERACCESS0)
79
MDIO User Access Register 0 (USERACCESS0) Field Descriptions
79
MDIO User PHY Select Register 0 (USERPHYSEL0)
80
MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions
80
MDIO User Access Register 1 (USERACCESS1)
81
MDIO User Access Register 1 (USERACCESS1) Field Descriptions
81
MDIO User PHY Select Register 1 (USERPHYSEL1)
82
MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
82
EMAC Module Registers
83
Ethernet Media Access Controller (EMAC) Registers
83
Transmit Revision ID Register (TXREVID)
86
Transmit Control Register (TXCONTROL)
86
Transmit Revision ID Register (TXREVID) Field Descriptions
86
Transmit Control Register (TXCONTROL) Field Descriptions
86
Transmit Teardown Register (TXTEARDOWN)
87
Transmit Teardown Register (TXTEARDOWN) Field Descriptions
87
Receive Revision ID Register (RXREVID)
88
Receive Control Register (RXCONTROL)
88
Receive Revision ID Register (RXREVID) Field Descriptions
88
Receive Control Register (RXCONTROL) Field Descriptions
88
Receive Teardown Register (RXTEARDOWN)
89
Receive Teardown Register (RXTEARDOWN) Field Descriptions
89
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW)
90
Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions
90
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED)
91
Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions
91
Transmit Interrupt Mask Set Register (TXINTMASKSET)
92
Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions
92
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR)
93
Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions
93
MAC Input Vector Register (MACINVECTOR)
94
MAC Input Vector Register (MACINVECTOR) Field Descriptions
94
MAC End of Interrupt Vector Register (MACEOIVECTOR)
95
MAC End of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions
95
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW)
96
Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions
96
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
97
Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
97
Receive Interrupt Mask Set Register (RXINTMASKSET)
98
Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
98
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)
99
Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions
99
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW)
100
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED)
100
MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions
100
MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions
100
MAC Interrupt Mask Set Register (MACINTMASKSET)
101
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
101
MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
101
MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
101
Descriptions
101
Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE)
102
Receive Unicast Enable Set Register (RXUNICASTSET)
105
Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions
105
Receive Unicast Clear Register (RXUNICASTCLEAR)
106
Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions
106
Receive Maximum Length Register (RXMAXLEN)
107
Receive Buffer Offset Register (RXBUFFEROFFSET)
107
Receive Maximum Length Register (RXMAXLEN) Field Descriptions
107
Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions
107
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)
108
Receive Channel Flow Control Threshold Registers (RX0FLOWTHRESH-RX7FLOWTHRESH)
108
Receive Channel N Flow Control Threshold Register (Rxnflowthresh)
108
Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions
108
Receive Channel N Flow Control Threshold Register (Rxnflowthresh) Field Descriptions
108
Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER)
109
Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
109
Receive Channel N Free Buffer Count Register (Rxnfreebuffer) Field Descriptions
109
MAC Control Register (MACCONTROL)
110
MAC Control Register (MACCONTROL) Field Descriptions
110
MAC Status Register (MACSTATUS)
112
MAC Status Register (MACSTATUS) Field Descriptions
112
Emulation Control Register (EMCONTROL)
114
FIFO Control Register (FIFOCONTROL)
114
Emulation Control Register (EMCONTROL) Field Descriptions
114
FIFO Control Register (FIFOCONTROL) Field Descriptions
114
MAC Configuration Register (MACCONFIG)
115
Soft Reset Register (SOFTRESET)
115
MAC Configuration Register (MACCONFIG) Field Descriptions
115
Soft Reset Register (SOFTRESET) Field Descriptions
115
MAC Source Address Low Bytes Register (MACSRCADDRLO)
116
MAC Source Address High Bytes Register (MACSRCADDRHI)
116
MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions
116
MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions
116
MAC Hash Address Register 1 (MACHASH1)
117
MAC Hash Address Register 2 (MACHASH2)
117
MAC Hash Address Register 1 (MACHASH1) Field Descriptions
117
MAC Hash Address Register 2 (MACHASH2) Field Descriptions
117
Back off Test Register (BOFFTEST)
118
Transmit Pacing Algorithm Test Register (TPACETEST)
118
Back off Random Number Generator Test Register (BOFFTEST)
118
Back off Test Register (BOFFTEST) Field Descriptions
118
Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions
118
Receive Pause Timer Register (RXPAUSE)
119
Transmit Pause Timer Register (TXPAUSE)
119
Receive Pause Timer Register (RXPAUSE) Field Descriptions
119
Transmit Pause Timer Register (TXPAUSE) Field Descriptions
119
MAC Address Low Bytes Register (MACADDRLO)
120
MAC Address Low Bytes Register (MACADDRLO) Field Descriptions
120
MAC Address High Bytes Register (MACADDRHI)
121
MAC Index Register (MACINDEX)
121
MAC Address High Bytes Register (MACADDRHI) Field Descriptions
121
MAC Index Register (MACINDEX) Field Descriptions
121
Transmit Channel DMA Head Descriptor Pointer Registers (TX0HDP-TX7HDP)
122
Receive Channel DMA Head Descriptor Pointer Registers (RX0HDP-RX7HDP)
122
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp)
122
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp)
122
Transmit Channel N DMA Head Descriptor Pointer Register (Txnhdp) Field Descriptions
122
Receive Channel N DMA Head Descriptor Pointer Register (Rxnhdp) Field Descriptions
122
Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)
123
Receive Channel Completion Pointer Registers (RX0CP-RX7CP)
123
Transmit Channel N Completion Pointer Register (Txncp)
123
Receive Channel N Completion Pointer Register (Rxncp)
123
Transmit Channel N Completion Pointer Register (Txncp) Field Descriptions
123
Receive Channel N Completion Pointer Register (Rxncp) Field Descriptions
123
5.50 Network Statistics Registers
124
Statistics Register
124
Appendix A Glossary
133
Physical Layer Definitions
134
Appendix B Revision History
135
Document Revision History
135
Important Notice
136
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