ST STM32L4+ Series Reference Manual page 1460

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General-purpose timers (TIM15/TIM16/TIM17)

Bits 31:2 Reserved, must be kept at reset value.

Bits1:0 TI1_RMP[1:0]: Input capture 1 remap

00: TIM17 input capture 1 is connected to I/O

01: TIM17 input capture 1 is connected to MSI

10: TIM17 input capture 1 is connected to HSE/32

11: TIM17 input capture 1 is connected to MCO

TIM17 option register 2 (TIM17_OR2)

Address offset: 0x60

Reset value: 0x0000 0001

Bits 31:12 Reserved, must be kept at reset value.

Bit 11 BKCMP2P: BRK COMP2 input polarity

This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP

polarity bit.

0: COMP2 input is active low

1: COMP2 input is active high

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits

Bit 10 BKCMP1P: BRK COMP1 input polarity

This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP

polarity bit.

0: COMP1 input is active low

1: COMP1 input is active high

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits

Bit 9 BKINP: BRK BKIN input polarity

This bit selects the BKIN alternate function input sensitivity. It must be programmed together

with the BKP polarity bit.

0: BKIN input is active low

1: BKIN input is active high

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits

Bit 8 BKDF1BK2E: BRK dfsdm1_break[2] enable

This bit enables the dfsdm1_break[2] for the timer's BRK input. dfsdm1_break[2] output is

'ORed' with the other BRK sources.

0: dfsdm1_break[2] input disabled

1: dfsdm1_break[2] input enabled

Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits

in TIMx_BDTR register).

RM0432 Rev 6

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