Clock Asynchronous Serial I/O (Uart) Mode - Renesas M16C Series Hardware Manual

R8C/11 Group

13.2 Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired bit rate and transfer data
format. Tables 13.4 lists the specifications of the UART mode. Table 13.5 lists the registers and settings
for UART mode.
Table 13.4 UART Mode Specifications
Item
Transfer data format
Transfer clock
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
NOTES:
1. If an overrun error occurs, the value of U0RB register will be indeterminate. The IR bit in the S0RIC register does
not change.
Rev.1.20 Jan 27, 2006
REJ09B0062-0120
• Character bit (transfer data): selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: selectable from odd, even, or none
• Stop bit: selectable from 1 or 2 bits
• UiMR(i=0, 1) register CKDIR bit = 0 (internal clock) : fj/(16(n+1))
fj=f , f , f
1SIO 8SIO 32SIO
• CKDIR bit = "1" (external clock) : f
f : input from CLKi pin
EXT
• Before transmission can start, the following requirements must be met
_
TE bit in UiC1 register= 1 (transmission enabled)
_
TI bit in UiC1 register = 0 (data present in UiTB register)
• Before reception can start, the following requirements must be met
_
RE bit in UiC1 register= 1 (reception enabled)
_
Start bit detection
• For transmission, one of the following conditions can be selected
_
UiIRS bit = 0 (transmit buffer empty): when transferring data from UiTB register to
UARTi transmit register (at start of transmission)
_
UiIRS bit =1 (transfer completed): when serial interface finished sending data from
UARTi transmit register
• For reception
When transferring data from UARTi receive register to UiRB register (at completion
of reception)
(1)
• Overrun error
This error occurs if serial interface started receiving the next data before reading
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1's in parity and character
bits does not match the number of 1's set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
• T D , R D selection (UART)
X 10 X 1
P3 pin can be used as RxD
7
• TxD pin selection (UART1)
11
P0 pin can be used as TxD
0
page 119 of 204
13.2 Clock Asynchronous Serial I/O (UART) Mode
Specification
n=setting value in UiBRG register: 00
/(16(n+1))
EXT
n=setting value in UiBRG register: 00
pin or TxD pin in UART1. Select by a program.
1 10
pin in UART1 or port P0
11
to FF
16 16
to FF
16 16
. Select by a program.
0