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o r
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13.1.2. Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 13.1.2.1 lists the specifications of the UART mode.
Table 13.1.2.1. UART Mode Specifications
Item
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
data from
Error detection
Select function
NOTES:
1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains
unchanged.
2. The U0IRS and U1IRS bits respectively are the bits "0" and "1" in the UCON register; the U2IRS bit is the bit 4 in
the U2C1 register.
R
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2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
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6
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• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
• The CKDIR bit in the UiMR(i=0 to 2) register is set to "0" (internal clock) : fj/(16(n+1))
fj = f
, f
1SIO
2SIO
• CKDIR bit is set to "1" (external clock ) : f
f
: Input from CLKi pin.
EXT
• Selectable from CTS function, RTS function or CTS/RTS function disable
• Before transmission can start, the following requirements must be met
_
The TE bit in the UiC1 register is set to "1" (transmission enabled)
_
The TI bit in the UiC1 register "0" (data present in UiTB register)
_______
_
If CTS function is selected, input "L" to the CTSi pin
• Before reception can start, the following requirements must be met
_
The RE bit in the UiC1 register is set to "1" (reception enabled)
_
Start bit detection
• For transmission, one of the following conditions can be selected
_
The UiIRS bit
UiTB register to the UARTi transmit register (at start of transmission)
_
The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error
This error occurs when if parity is enabled, the number of 1's in parity and
character bits does not match the number of 1's set
• Error sum flag
This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Serial data logic switch (UART2)
This function reverses the logic of the transmit/receive data. The start and stop bits
are not reversed.
• T
D, R
D I/O polarity switch (UART2)
X
X
This function reverses the polarities of hte T
logic levels of all I/O data is reversed.
_______ _______
• Separate CTS/RTS pins (UART0)
_________
_________
CTS
and RTS
0
• UART1 pin remapping selection
The UART1 pin can be selected from the P6
page 150
f o
3
2
9
6
C
2 /
6
) T
Specification
, f
, f
. n: Setting value of UiBRG register
8SIO
32SIO
n :Setting value of UiBRG register
_______
_______
(2)
is set to "0" (transmit buffer empty): when transferring data from the
(1)
are input/output from separate pins
0
/(16(n+1))
EXT
00
_______ _______
_______
D pin output and R
D pin input. The
X
X
to P6
or P7
to P7
.
7
4
3
0
13. Serial I/O
00
to FF
16
16
to FF
16
16
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