Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1710

Functional Description
Table 29-1: ADSP-SC58x PCIE Register List (Continued)
Name
PCIE_DMA_CTL_[n]
PCIE_DMA_VWPRT_SEL_[n]
PCIE_EP_BAR0_MASK[n]
PCIE_EP_BAR0_[n]
PCIE_EP_BAR1_MASK[n]
PCIE_EP_BAR1_[n]
PCIE_EP_BAR2_MASK[n]
PCIE_EP_BAR2_[n]
PCIE_EP_BAR3_MASK[n]
PCIE_EP_BAR3_[n]
PCIE_EP_BAR4_MASK[n]
PCIE_EP_BAR4_[n]
PCIE_EP_BAR5_MASK[n]
PCIE_EP_BAR5_[n]
PCIE_EP_CAPBPTR_[n]
PCIE_EP_CCRID_[n]
PCIE_EP_CFG_[n]
PCIE_EP_CRDBPTR_[n]
PCIE_EP_DEVCAPB_[n]
PCIE_EP_ID_[n]
PCIE_EP_PINLN_INT_[n]
PCIE_EP_ROMCFG_[n]
PCIE_EP_SSVID_[n]
PCIE_EP_STATCMD_[n]
PCIE_ERRSRC_ID_[n]
PCIE_FILTMSK2_[n]
PCIE_GEN2_CTL_[n]
PCIE_HDRLOG0_[n]
PCIE_HDRLOG1_[n]
PCIE_HDRLOG2_[n]
PCIE_HDRLOG3_[n]
29–6
Description
DMA Number of Channels Register
DMA Channel Context Index Register
Endpoint Base Address Mask Register 0
Endpoint Base Address Register 0
Endpoint Base Address Mask Register 1
Endpoint Base Address Register 1
Endpoint Base Address Mask Register 2
Endpoint Base Address Register 2
Endpoint Base Address Mask Register 3
Endpoint Base Address Register 3
Endpoint Base Address Mask Register 4
Endpoint Base Address Register 4
Endpoint Base Address Mask Register 5
End Point Base Address Register 5
Capability Pointer Register
Class Code and Revision ID Register
End Point Configuration Register
CardBus CIS Pointer Register
Device Capabilities Register
Device ID and Vendor ID Register
Interrupt Line and Pin Register
End Point Expansion ROM Base Address Register
Subsystem ID and Subsystem Vendor ID Register
Command and Status Register
Error Source Identification Register
Filter Mask 2 Register
Link Width and Speed Change Control Register
Header Log Register 0
Header Log Register 1
Header Log Register 2
Header Log Register 3
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference