Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.6.9 Hardware trigger wait mode (select mode, sequential conversion mode)

<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
hardware trigger standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts. (At this time, no hardware trigger is necessary.)
<4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 9-25. Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
<1> ADCE is set to 1.
ADCE
Hardware
trigger
Trigger
The trigger
is not
standby
acknowledged.
status
ADCS
ADS
A/D
Stop status
conversion
status
ADCR,
ADCRH
INTAD
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Operation Timing
A hardware trigger
<2> <4>
is generated.
ANI0
<3> A/D conversion ends
and the next conversion
starts. <3>
Data 1 Data 2 Data 3
(ANI0) (ANI0) (ANI0)
A/D power supply
stabilization wait
Data 1 Data 2
(ANI0) (ANI0)
A hardware trigger is
generated during A/D
conversion operation.
ADCS is overwritten
with 1 during A/D
conversion operation.
ADS is rewritten during
<5>
A/D conversion operation
(from ANI0 to ANI1).
Conversion is
Conversion is
interrupted interrupted
<3>
and restarts. and restarts.
Data 5 Data 6
Data 4
(ANI0) (ANI0) (ANI1)
Data 4
(ANI0)
CHAPTER 9 A/D CONVERTER
Trigger
standby
status
ADCS is cleared
<6> <7>
to 0 during A/D
conversion operation.
ANI1
Conversion is
interrupted
Conversion is
<3> and restarts. <3>
interrupted.
Data 7 Data 8 Data 9
Stop status
(ANI1) (ANI1) (ANI1)
Data 6 Data 8
(ANI1) (ANI1)
The trigger
is not
acknowledged.
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