Renesas RL78/G1P Hardware User Manual page 426

RL78/G1P
(Essential)
(Selective)
(Selective)
Changing setting of the SPSm register
(Selective)
Changing setting of the SDRmn register
(Selective)
Changing setting of the SMRmn register
(Selective)
Changing setting of the SCRmn register
(Selective)
(Selective)
Changing setting of the SOEm register
(Essential)
(Essential)
Changing setting of the SOEm register
(Essential)
(Essential)
(Essential)
(Essential)
Remark m: Unit number (m = 0), n: Channel number (n = 0), p: CSI number (p = 00)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 11-80. Procedure for Resuming Slave Transmission
Starting setting for resumption
Completing master
preparations?
Yes
Port manipulation
Clearing error flag
Changing setting of the SOm register
Port manipulation
Writing to the ISC register
Writing to the SSm register
Starting communication
Completing resumption setting
Wait until stop the communication target (master)
No
or operation completed.
Disable data output of the target channel by setting
a port register and a port mode register.
Re-set the register to change the operation clock
setting.
Re-set the register to change the transfer baud
rate setting (setting the transfer clock by dividing
the operation clock (f
Re-set the register to change serial mode register
mn (SMRmn) setting.
Re-set the register to change serial communication
operation setting register mn (SCRmn) setting.
If the OVF flag remains set, clear this
using serial flag clear trigger register mn
(SIRmn).
Set the SOEmn bit to 0 to stop output from the
target channel.
Set the initial output level of the serial data
(SOmn).
Set the SOEmn bit to 1 and enable output from the
target channel.
Enable data output of the target channel by
setting a port register and a port mode register.
When connecting multiple slaves, set N-ch open-
drain before setting data output.
Set the SSIE00 bit to 1 and enable slave select
function operation of channel 0.
Set the SSmn bit of the target channel to 1
(SEmn = 1: to enable operation).
Sets transmit data to the SIOp register (bits 7 to 0
of the SDRmn register) and wait for a clock from
the master.
CHAPTER 11 SERIAL ARRAY UNIT
)).
MCK
407