Renesas RL78/G1P Hardware User Manual page 288

RL78/G1P
Figure 9-15. Conversion Operation of A/D Converter (Software Trigger Mode)
ADCS  1 or ADS rewrite
A/D converter
SAR clear
operation
SAR
Undefined
ADCR
INTAD
In one-shot conversion mode, the ADCS bit is automatically cleared to 0 after completion of A/D conversion.
In sequential conversion mode, A/D conversion operations proceed continuously until the software clears bit 7 (ADCS)
of the A/D converter mode register 0 (ADM0) to 0.
Writing to the analog input channel specification register (ADS) during A/D conversion interrupts the current conversion
after which A/D conversion of the analog input specified by the ADS register proceeds. Data from the A/D conversion that
was in progress are discarded.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Sampling time
Sampling
Conversion time
A/D conversion
CHAPTER 9 A/D CONVERTER
Conversion
result
Conversion
result
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