Renesas RL78/G1P Hardware User Manual page 671

16-bit single-chip microcontroller
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RL78/G1P
20.7 SFR guard function
In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from
being overwritten, even if the CPU freezes.
This SFR guard function is used to protect data in the control registers used by the port function, interrupt function,
clock control function, voltage detection function, and RAM parity error detection function.
If the SFR guard function is specified, writing to the specified SFRs is disabled, but reading from the SFRs can be
carried out as usual.
20.7.1 Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard function.
GPORT, GINT and GCSC bits are used in SFR guard function.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 20-10. Format of Invalid Memory Access Detection Control Register (IAWCTL)
Address: F0078H
After reset: 00H
Symbol
7
IAWCTL
IAWEN
GPORT
0
1
GINT
0
1
Note 3
GCSC
0
1
Notes 1.
24-pin products only
2.
Pxx (Port register) is not guarded.
3.
Clear GCSC bit to 0, during self programming /serial programming.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
R/W
6
5
0
GRAM1
Disabled. Control registers of port function can be read or written to.
Enabled. Writing to control registers of port function is disabled. Reading is enabled.
[Guarded SFR] PMxx, PUxx, PMC1
Disabled. Registers of interrupt function can be read or written to.
Enabled. Writing to registers of interrupt function is disabled. Reading is enabled.
[Guarded SFR] IFxx, MKxx, PRxx, EGP0, EGN0
Control registers of clock control function, voltage detector and RAM parity error detection function guard
Disabled. Control registers of clock control function, voltage detector and RAM parity error detection
function can be read or written to.
Enabled. Writing to control registers of clock control function, voltage detector and RAM parity error
detection function is disabled. Reading is enabled.
[Guarded SFR] CMC, CSC, OSTS, CKC, PERx, LVIM, LVIS, RPECTL
CHAPTER 20 SAFETY FUNCTIONS
4
3
GRAM0
0
Control registers of port function guard
Note 1
Note 2
, ADPC
Registers of interrupt function guard
2
1
GPORT
GINT
0
GCSC
652

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