Renesas RL78/G1P Hardware User Manual page 630

16-bit single-chip microcontroller

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Reset times (times for release from the external reset state)

After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use.

After the second release of the POR: 0.531 ms (typ.), 0.675 ms (max.) when the LVD is in use.

After power is supplied, a voltage stabilization waiting time of about 0.99 ms (typ.) and up to 2.30 ms (max.)

is required before reset processing starts after release of the external reset.

2. The state of P40 is as follows.

 High-impedance during the external reset period or reset period by the POR.

 High level during other types of reset or after receiving a reset signal (connected to the on-chip pull-up

resistance).

Caution A watchdog timer internal reset resets the watchdog timer.

Remark For the reset timing of the power-on-reset circuit and voltage detector, see CHAPTER 18 POWER-ON-

RESET CIRCUIT and CHAPTER 19 VOLTAGE DETECTOR.

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

0.399 ms (typ.), 0.519 ms (max.) when the LVD is off.

0.259 ms (typ.), 0.362 ms (max.) when the LVD is off.

CHAPTER 17 RESET FUNCTION