Renesas RL78/G1P Hardware User Manual page 503

RL78/G1P
2
12.4 I C Bus Mode Functions
12.4.1 Pin configuration
The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows.
(1) SCLAn .... This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
(2) SDAAn .... This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
resistor is required.
Master device
Clock output
(Clock input)
Data output
Data input
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-13. Pin Configuration Diagram
SCLAn
V
SS
SDAAn
V
SS
CHAPTER 12 SERIAL INTERFACE IICA
V
DD
SCLAn
V
DD
SDAAn
Slave device
(Clock output)
V
SS
Clock input
Data output
V
SS
Data input
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