Renesas RL78/G1P Hardware User Manual page 668

RL78/G1P
20.5 RAM parity error detection function
The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data
in the RAM of the RL78/G1P. By using this RAM parity error detection function, the parity bit is appended when data is
written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity
error occurs.
20.5.1 RAM parity error control register (RPECTL)
This register is used to control parity error generation check bit and reset generation due to parity errors.
The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 20-7. Format of RAM Parity Error Control Register (RPECTL)
Address: F00F5H After reset: 00H
Symbol <7>
RPECTL RPERDIS
RPERDIS
0
1
RPEF
0
1
Caution The parity bit is appended when data is written, and the parity is checked when the data is read.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas
where data access is to proceed before reading data.
The RL78's CPU executes look-ahead due to the pipeline operation, the CPU might read an
uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM
area + 10 bytes when instructions are fetched from RAM areas. When using the self-programming
function while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM area
to overwrite + 10 bytes before overwriting.
Remarks 1. The RAM parity check is always on, and the result can be confirmed by checking the PREF flag.
2. The parity error reset is enabled by default (RPERDIS = 0).
Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity error
occurs.
3. The RPEF flag is set (1) by RAM parity errors and cleared (0) by writing 0 to it or by any reset source.
When RPEF = 1, the value is retained even if RAM for which no parity error has occurred is read.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
R/W
6 5
0 0
Enable parity error resets.
Disable parity error resets.
No parity error has occurred.
A parity error has occurred.
CHAPTER 20 SAFETY FUNCTIONS
4 3
0 0
Parity error reset mask flag
Parity error status flag
2 1
0 0 RPEF
<0>
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