Renesas RL78/G1P Hardware User Manual page 140

RL78/G1P
Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/3)
(3) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(B)  (C)
(X1 clock: 1 MHz  fX  10 MHz)
(B)  (C)
(X1 clock: 10 MHz < fX  20 MHz)
(B)  (C)
(external main clock)
Notes 1. The clock operation mode control register (CMC) can be changed only once after reset release. This
setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
 Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time 
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS).
Remarks 1. ×: don't care
2. (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14.
(4) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(C)  (B)
Remarks 1. (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14
2. The oscillation accuracy stabilization time changes according to the temperature conditions and the
STOP mode period.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CMC Register
Note 1
EXCLK OSCSEL AMPH
0 1 0
0 1 1

1 1
Unnecessary if these registers
are already set
CSC Register
HIOSTOP
0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
CHAPTER 5 CLOCK GENERATOR
OSTS CSC OSTC Register
Register Register
MSTOP
0 Must be checked
Note 2
0 Must be checked
Note 2
0 Must not be checked
Note 2
Unnecessary if the CPU is operating with
the high-speed system clock
Oscillation accuracy
stabilization time
18 μs to 65 μs
CKC
Register
MCM0
1
1
1
CKC Register
MCM0
0
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