Operation Of Counter; Count Clock (F ) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.5 Operation of Counter

6.5.1 Count clock (f )
TCLK
The count clock (f ) of the timer array unit can be selected between following by CCSmn bit of timer mode register
TCLK
mn (TMRmn).
 Operation clock (f
MCK
 Valid edge of input signal input from the TImn pin
Because the timer array unit is designed to operate in synchronization with f
are shown below.
(1) When operation clock (f
The count clock (f
divided f is selected, however, the clock selected in TPSmn register, but a signal which becomes high level for
CLK
one period of f from its rising edge. When a f
CLK
Counting of timer count register mn (TCRmn) delayed by one period of f
because of synchronization with f
matter of convenience.
Figure 6-23. Timing of f
f
CLK
f
CLK
f
CLK
f
TCLK
f
( = f
CLK
MCK
= CKmn)
f
CLK
Remarks 1.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
) specified by the CKSmn0 and CKSmn1 bits
) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0)
MCK
) is between f to f
TCLK CLK
. But, this is described as "counting at rising edge of the count clock", as a
CLK
CLK
/2
/4
/8
/16
: Rising edge of the count clock
: Synchronization, increment/decrement of counter
f : CPU/peripheral hardware clock
2.
CLK
/2 15 by setting of timer clock select register m (TPSm). When a
CLK
is selected, fixed to high level
CLK
and Count Clock (f ) (When CCSmn = 0)
TCLK
CHAPTER 6 TIMER ARRAY UNIT
, the timings of the count clock (f
CLK
from rising edge of the count clock,
CLK
)
TCLK
161