Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)

<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
hardware trigger standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is initialized.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 9-26. Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
<1> ADCE is set to 1.
ADCE
A hardware trigger
<2>
is generated.
Hardware
trigger
Trigger
The trigger is not
ADCS is automatically
standby
acknowledged.
cleared to 0 after
status
conversion ends.
ADCS
ANI0
ADS
A/D
Data 1
conversion
Stop status
(ANI0)
status
A/D power supply
stabilization wait
ADCR,
ADCRH
INTAD
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Operation Timing
A hardware trigger is
<5>
generated during A/D
<2>
conversion operation.
<4> <4>
Conversion is
<3> A/D conversion ends.
interrupted <3>
and restarts.
Stop Data 2
Data 3
Stop status
status (ANI0) (ANI0)
A/D power supply
stabilization wait
Data 2
(ANI0)
CHAPTER 9 A/D CONVERTER
<2> <2>
<4> <7>
<6> ADS is rewritten
during A/D conversion
operation (from ANI0
to ANI1).
ANI1
Conversion
is interrupted <3>
and restarts.
Data 4 Data 5
Data 6
Stop status
(ANI0) (ANI1) (ANI1)
A/D power supply A/D power supply
stabilization wait stabilization wait
Data 3
(ANI0)
Trigger
<2>
standby
status
ADCS is cleared
ADCS is overwritten <8>
<4>
to 0 during A/D
with 1 during A/D
conversion
conversion operation.
operation.
Conversion is
Conversion is
interrupted <3>
interrupted.
and restarts.
Data 7 Stop Data 8
Stop status
(ANI1) status (ANI1)
A/D power supply
stabilization wait
Data 5 Data 7
(ANI1) (ANI1)
The trigger is not
acknowledged.
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