Renesas RL78/G1P Hardware User Manual page 271

RL78/G1P
(2) A/D conversion times for 12-bit A/D conversion when there is power supply stabilization wait time
(for hardware trigger wait mode (except for the second and subsequent conversions
in sequential conversion mode and conversion of the channels specified for scan 1, 2, and 3 in scan mode
A/D Converter Mode Mode
Register 0 (ADM0)
FR2 FR1 FR0 LV0
0 0 0 0 Normal
1
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 1 Normal
2
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Notes 1. For the second and subsequent conversion in sequential conversion mode and for conversion of the channel
specified by scan 1, 2, and 3 in scan mode, the A/D power supply stabilization wait time do not occur after a
hardware trigger is detected (see Table 9-3 (1/4)).
2. When using ANI16, setting this value is prohibited.
Cautions 1. The A/D conversion time must also be within the relevant range of conversion times (t
described in 27.6.1 A/D converter characteristics.
Note that the conversion time (t
2. Rewrite the FR2 to FR0 and LV0 bits to other than the same data while conversion is stopped (ADCS =
0, ADCE = 0).
3. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
4. In hardware trigger wait mode, make settings that affect the conversion time such that the following
conditions are satisfied.
 f
must be in the range from 1 to 16 MHz.
AD
 When the setting of the ADISS bit of the ADS register is 1, selecting the temperature sensor or
internal reference voltage output, the following condition applies.
Setting LV0 to 0 is prohibited.
Only setting LV0 to 1 is permitted.
Remark f : CPU/peripheral hardware clock frequency
CLK
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 9-3. A/D Conversion Time Selection (2/4)
Conversion Number of Number of
Clock (f ) A/D Power Conversion
AD
Supply Clock
Stabilization (Number of
Wait Clock Sampling
Clock)
f /32 4 f 54 f
CLK CLK AD
(number of
sampling
f /16
CLK
clock:
11 f
AD
f /8
CLK
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1 2 f
CLK CLK
f /32 58 f 66 f
CLK CLK AD
(number of
sampling
f /16
CLK
clock:
f /8
CLK
23 f
AD
f /6
CLK
f /5
CLK
f /4
CLK
f /2
CLK
f /1 29 f
CLK CLK
) does not include the A/D power supply stabilization wait time.
CONV
A/D Power Selected A/D Power Supply Stabilization Wait Times
Supply
Stabilization
Wait Time +
f = 1
Conversion
CLK
MHz
Time
1732/f Setting
CLK
prohibited
868/f
CLK
)
436/f
CLK
328/f
CLK
274/f
CLK
220/f
CLK
112/f
CLK

56/f
56 s
Note 2
CLK
2170/f Setting
CLK
prohibited
1114/f
CLK
586/f
CLK
)
454/f
CLK
388/f
CLK
322/f
CLK
190/f
CLK

95/f
95 s
Note 2
CLK
CHAPTER 9 A/D CONVERTER
+ Conversion Times
AV = 2.7 to 3.6 V
DD
f = 4 f = 8 f = 16
CLK CLK CLK
MHz MHz MHz
Setting Setting Setting
prohibited prohibited prohibited

54.25
Note 2
 
54.5 s 27.25
Note 2 Note 2
 
41 s 20.5 s
Note 2
Note 2
 s  s
34.25 17.125
Note 2 Note 2
  
55 s 27.5 s 13.75
Note 2
Note 2 Note 2
  
28 s 14 s 7 s
Note 2 Note 2 Note 2
  
14 s 7 s 3.5 s
Note 2 Note 2 Note 2
Setting Setting Setting
prohibited prohibited prohibited

69.625
 
73.25 s 36.625
Note 2
 
56.75 s 28.375
Note 2
 
48.5 s 24.25
Note 2
  
80.5 s 40.25 s 20.125
Note 2 Note 2
 

47.5 s 23.75 s 11.875
Note 2 Note 2
  
23.75 s 11.875 s 5.9375
Note 2 Note 2
CONV
))
Note 1
f = 32
CLK
MHz

54.125 s
Note 2

s 27.125 s
Note 2

s 13.625 s
Note 2

10.25 s
Note 2

8.5625 s
Note 2

s 6.875 s
Note 2

3.5 s
Note 2
Setting
prohibited

67.8125 s

s 34.8125 s

s 18.3125 s

s 14.1875 s

s 12.125 s

s 10.0625 s

s 5.9375 s
Setting
s
prohibited
)
252