RL78/G1P
11.5.2 Master reception
Master reception is that the RL78/G1P outputs a transfer clock and receives data from other device.
3-Wire Serial I/O
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Note
Transfer rate
Data phase
Clock phase
Data direction
Note
Use this operation within a range that satisfies the conditions above and the peripheral functions characteristics in
the electrical specifications (see CHAPTER 27 ELECTRICAL SPECIFICATIONS).
Remark
m: Unit number (m = 0), n: Channel number (n = 0), mn = 00
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Channel 0 of SAU0
SCK00, SI00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. f
/2 [Hz]
MCK
/(2 2
128) [Hz]
15
Min. f
CLK
Selectable by the DAPmn bit of the SCRmn register
DAPmn = 0: Data input starts from the start of the operation of the serial clock.
DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Selectable by the CKPmn bit of the SCRmn register
CKPmn = 0: Non-reverse
CKPmn = 1: Reverse
MSB or LSB first
CHAPTER 11 SERIAL ARRAY UNIT
CSI00
f
: System clock frequency
CLK
350