Renesas RL78/G1P Hardware User Manual page 566

16-bit single-chip microcontroller

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(8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)

(3) Data ~ data ~ stop condition

(ACK detection)

(8 or 9 clock wait)

(ACK control)

(communication status)

(ST trigger)

(SP trigger)

(wait cancellation)

(transmit/receive)

(clock line)

(ACK detection)

(ST detection)

(SP detection)

(8 or 9 clock wait)

(ACK control)

(communication

(wait cancellation)

(transmit/receive)

Notes 1. To cancel a wait state, write "FFH" to IICAn or set the WRELn bit.

2. Make sure that the time between the rise of the SCLAn pin signal and the generation of the stop

condition after a stop condition has been issued is at least 4.0

3. Write data to IICAn, not setting the WRELn bit, in order to cancel a wait state during transmission by a

slave device.

4. If a wait state during transmission by a slave device is canceled by setting the WRELn bit, the TRCn bit

will be cleared.

Remark n = 0, 1

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

Figure 12-33. Example of Slave to Master Communication

: Wait state by master device

: Wait state by slave device

: Wait state by master and slave devices

s when specifying fast mode.

CHAPTER 12 SERIAL INTERFACE IICA

Stop condition

s when specifying standard mode and at