Renesas RL78/G1P Hardware User Manual page 75

RL78/G1P
[HL + byte],
<1> <2>
Instruction code
OP-code
<2>
Either pair of registers <1> specifies the address
where the target array of data starts in the 64 KB
area from F0000H to FFFFFH.
"byte" <2> specifies an offset within the array to
the target location in memory.
word [B],
<1> <2>
Instruction code
OP-code
Low Addr.
High Addr.
"word" <1> specifies the address where the target
array of word-sized data starts in the 64 KB area
from F0000H to FFFFFH.
Either register <2> specifies an offset within the
array to the target location in memory.
word [BC]
<1> <2>
Instruction code
OP-code
Low Addr.
<1>
High Addr.
"word" <1> specifies the address where the target
array of word-sized data starts in the 64 KB area
from F0000H to FFFFFH.
A pair of registers <2> specifies an offset within
the array to the target location in memory.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 3-24. Example of [HL+byte], [DE+byte]
[DE + byte]
<1> <2>
byte
rp(HL/DE)
Figure 3-25. Example of word[B], word[C]
word [C]
<1> <2>
<2>
r(B/C)
<1>
Figure 3-26. Example of word[BC]
<2>
rp(BC)
<1>
<2>
Offset
<1>
Address of
an array
<2>
Offset
Address of a word
within an array
Target memory
<2>
Offset
Address of a word
within an array
CHAPTER 3 CPU ARCHITECTURE
FFFFFH
Target memory
Other data in
the array
F0000H
Memory
FFFFFH
Target memory
F0000H
Memory
FFFFFH
Array of
word-sized
data
F0000H
Memory
Target
array
of data
Array of
word-sized
data
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