Start Timing Of Counter - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.5.2 Start timing of counter

Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register
m (TSm).
Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 6-5.
Table 6-5. Operations from Count Operation Enabled State to Timer count Register mn (TCRmn) Count Start
Timer Operation Mode
 Interval timer mode
 Event counter mode
 Capture mode
 One-count mode
 Capture & one-count mode
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Operation When TSmn = 1 Is Set
No operation is carried out from start trigger detection (TSmn=1) until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
6.5.3 (1) Operation of interval timer mode).
Writing 1 to the TSmn bit loads the value of the TDRmn register to the TCRmn
register.
If detect edge of TImn input. The subsequent count clock performs count down
operation (see 6.5.3 (2) Operation of event counter mode).
No operation is carried out from start trigger detection (TSmn = 1) until count
clock generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 6.5.3 (3) Operation of capture
mode (input pulse interval measurement)).
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of the TDRmn register to the TCRmn
register and the subsequent count clock performs count down operation (see
6.5.3 (4) Operation of one-count mode).
The waiting-for-start-trigger state is entered by writing 1 to the TSmn bit while the
timer is stopped (TEmn = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCRmn register and the subsequent
count clock performs count up operation (see 6.5.3 (5) Operation of capture &
one-count mode (high-level interval measurement)).
CHAPTER 6 TIMER ARRAY UNIT
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