Renesas RL78/G1P Hardware User Manual page 507

RL78/G1P
12.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
matches the data values stored in the slave address register n (SVAn). If the address data matches the SVAn register
values, the slave device is selected and communicates with the master device until the master device generates a start
condition or stop condition.
SCLAn
SDAAn
INTIICAn
Note INTIICAn is not issued if data other than a local address or extension code is received during slave device
operation.
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in
12.5.3 Transfer direction specification are written to the IICA shift register n (IICAn). The received addresses are
written to the IICAn register.
The slave address is assigned to the higher 7 bits of the IICAn register.
12.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to
a slave device. When the transfer direction specification bit has a value of "1", it indicates that the master device is
receiving data from a slave device.
SCLAn
SDAAn
INTIICAn
Note INTIICAn is not issued if data other than a local address or extension code is received during slave device
operation.
Remark n = 0, 1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-16. Address
1 2 3 4
A6 A5 A4 A3
Address
Figure 12-17. Transfer Direction Specification
1 2 3 4
A6 A5 A4 A3
CHAPTER 12 SERIAL INTERFACE IICA
5 6 7 8
A2 A1 A0 R/W
5 6 7 8 9
A2 A1 A0 R/W
Transfer direction specification
9
Note
Note
488