Renesas RL78/G1P Hardware User Manual page 500

RL78/G1P
CLDn
0
1
Condition for clearing (CLDn = 0)
 When the SCLAn pin is at low level
 When IICEn = 0 (operation stop)
 Reset
DADn
0
1
Condition for clearing (DADn = 0)
 When the SDAAn pin is at low level
 When IICEn = 0 (operation stop)
 Reset
SMCn
0
1
DFCn
0
1
Digital filter can be used only in fast mode and fast mode plus.
In fast mode and fast mode plus, the transfer clock does not vary, regardless of the DFCn bit being set (1) or
cleared (0).
The digital filter is used for noise elimination in fast mode and fast mode plus.
PRSn
0
1
Caution
Remarks 1.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 12-9. Format of IICA Control Register n1 (IICCTLn1) (2/2)
Detection of SCLAn pin level (valid only when IICEn = 1)
The SCLAn pin was detected at low level.
The SCLAn pin was detected at high level.
Detection of SDAAn pin level (valid only when IICEn = 1)
The SDAAn pin was detected at low level.
The SDAAn pin was detected at high level.
Operates in standard mode (fastest transfer rate: 100 kbps).
Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1
Mbps).
Digital filter off.
Digital filter on.
Selects f as operation clock.
CLK
Selects f /2 as operation clock.
CLK
The fastest operation frequency of the operation clock of the serial interface IICA is 20
MHz (Max.). If the f
CLK
1.
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
2. n = 0, 1
CHAPTER 12 SERIAL INTERFACE IICA
Condition for setting (CLDn = 1)
 When the SCLAn pin is at high level
Condition for setting (DADn = 1)
 When the SDAAn pin is at high level
Operation mode switching
Digital filter operation control
Division of the operation clock
exceeds 20 MHz, set the clock to f /2 by setting the PRSn bit to
CLK
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