Timer Channel Stop Register M (Ttm) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.3.7 Timer channel stop register m (TTm)

The TTm register is a trigger register that is used to stop the counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared
to 0. The TTmn, TTHm1, TTHm3 bits are immediately cleared when operation is stopped (TEmn, TTHm1, TTHm3 = 0),
because they are trigger bits.
The TTm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TTm register can be set with a 1-bit or 8-bit memory manipulation instruction with TTmL.
Reset signal generation clears this register to 0000H.
Address: F01B4H, F01B5H (TT0)
Symbol 15 14
TTm 0 0
TTH
m3
0 No trigger operation
1 TEHm3 bit is cleared to 0 and the count operation is stopped.
TTH
m1
0 No trigger operation
1 TEHm1 bit is cleared to 0 and the count operation is stopped.
TTm
n
0 TEmn bit is cleared to 0 and the count operation is stopped.
1 TEmn bit clear to 0, to be count operation stop enable status.
This bit is the trigger to stop operation of the lower 8-bit timer for TTm1 and TTm3 when channel 1 or 3 is in
the 8-bit timer mode.
Caution Be sure to clear bits 15 to 12, 10, 8 to 4 to "0".
Remarks 1. When the TTm register is read, 0 is always read.
2. m: Unit number (m = 0),n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 6-15. Format of Timer Channel Stop register m (TTm)
After reset: 0000H R/W
13 12 11 10
0 0 TTHm 0 TTHm
3
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
Operation stop trigger of channel n
9 8 7 6
0 0 0
1
CHAPTER 6 TIMER ARRAY UNIT
5 4 3 2
0 0 TTm TTm TTm
3 2
1 0
TTm
1 0
150