Renesas RL78/G1P Hardware User Manual page 642

RL78/G1P
Figure 18-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
(3) When LVD is reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1)
Supply voltage (V
DD
V
LVD
Lower limit voltage for guaranteed operation
V = 1.50 V (TYP.)
PDR
V = 1.51 V (TYP.)
POR
0 V
High-speed on-chip
oscillator clock (f
IH
High-speed
system clock (f
MX
(when X1 oscillation
is selected)
CPU operation stops
Internal reset signal
Notes 1. The high-speed on-chip oscillator clock and a high-speed system clock can be selected as the CPU clock.
To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the
lapse of the oscillation stabilization time.
2. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed on-
chip oscillator clock.
3. The time until normal operation starts includes the following LVD reset processing time after the LVD
detection level (V
the V (1.51 V, typ.) is reached.
POR
LVD reset processing time: 0 ms to 0.0701 ms (max.)
4. When the power supply voltage is below the lower limit for operation and the power supply voltage is then
restored after an internal reset is generated only by the voltage detector (LVD), the following LVD reset
processing time is required after the LVD detection level (V
LVD reset processing time: 0.0511 ms (typ.), 0.0701 ms (max.)
Remarks 1. V :
LVD
V :
POR
V :
PDR
2. When the LVD interrupt mode is selected (option byte 000C1H: LVIMD1 = 0, LVIMD0 = 1), the time until
normal operation starts after power is turned on is the same as the time specified in Note 2 of Figure
18-2 (3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
and Voltage Detector (3/3)
)
Wait for oscillation
Note 2
accuracy stabilization
)
Starting oscillation is
specified by software
)
Normal operation
(high-speed on-chip
oscillator clock)
LVD reset processing time
Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.)
) is reached as well as the voltage stabilization wait + POR reset processing time after
LVD
LVD detection voltage
POR power supply rise detection voltage
POR power supply fall detection voltage
CHAPTER 18 POWER-ON-RESET CIRCUIT
Wait for oscillation
Note 2
accuracy stabilization
Starting oscillation is
specified by software
Reset
period
(oscillation
(oscillation stop)
Note 1 stop)
Note 3
LVD reset processing time
LVD
Wait for oscillation
accuracy stabilization
Starting oscillation is
specified by software
Normal operation
Reset period (high-speed on-chip
oscillator clock)
LVD reset processing time
Note 4
Voltage stabilization wait + POR reset processing time
1.64 ms (TYP.), 3.10 ms (MAX.)
) is reached.
Note 2
Note 1
Operation stops
Note 3
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