Renesas RL78/G1P Hardware User Manual page 636

RL78/G1P
The status of the RESF register when a reset request is generated is shown in Table 17-3.
Table 17-3. RESF Register Status When Reset Request Is Generated
Reset Source RESET Input
Flag
TRAP bit Cleared (0)
WDTRF bit
RPERF bit
IAWRF bit
LVIRF bit
Figure 17-5 shows the procedure for checking reset source.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Reset by Reset by
POR Execution of
Illegal
Instruction
Cleared (0) Set (1)
Held
CHAPTER 17 RESET FUNCTION
Reset by Reset by
WDT RAM Parity
Error
Held Held
Set (1)
Held Set (1)
Held
Reset by Reset by
Illegal- LVD
memory
Access
Held Held
Set (1)
Held Set (1)
617