Renesas RL78/G1P Hardware User Manual page 65

RL78/G1P
Address Extended Special Function Register
F01A0H Timer status register 00
F01A1H
F01A2H Timer status register 01
F01A3H
F01A4H Timer status register 02
F01A5H
F01A6H Timer status register 03
F01A7H
F01B0H Timer channel enable status register 0
F01B1H
F01B2H Timer channel start register 0
F01B3H
F01B4H Timer channel stop register 0
F01B5H
F01B6H Timer clock select register 0
F01B7H
F01B8H Timer output register 0
F01B9H
F01BAH Timer output enable register 0
F01BBH
F01BCH Timer output level register 0
F01BDH
F01BEH Timer output mode register 0
F01BFH
F0230H IICA control register 00
F0231H IICA control register 01
F0232H IICA low-level width setting register 0
F0233H IICA high-level width setting register 0
F0234H Slave address register 0
F0238H IICA control register 10
F0239H IICA control register 11
F023AH IICA low-level width setting register 1
F023BH IICA high-level width setting register 1
F023CH Slave address register 1
F02F0H Flash memory CRC control register
F02F2H Flash memory CRC operation result
register
F02FAH CRC data register
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Table 3-6. Extended Special Function Register (2nd SFR) List (3/4)
(2nd SFR) Name
CHAPTER 3 CPU ARCHITECTURE
Symbol R/W
TSR00L TSR00 R

TSR01L TSR01 R

TSR02L TSR02 R

TSR03L TSR03 R

TE0L TE0 R

TS0L TS0 R/W

TT0L TT0 R/W

TPS0 R/W
TO0L TO0 R/W

TOE0L TOE0 R/W

TOL0L TOL0 R/W

TOM0L TOM0 R/W

IICCTL00 R/W
IICCTL01 R/W
IICWL0 R/W
IICWH0 R/W
SVA0 R/W
IICCTL10 R/W
IICCTL11 R/W
IICWL1 R/W
IICWH1 R/W
SVA1 R/W
CRC0CTL R/W
PGCRCL R/W
CRCD R/W
Manipulable Bit Range
After Reset
1-bit 8-bit 16-bit
  
 
  
 
  
 
  
 
  
 
  
 
  
 
  
  
 
  
 
  
 
  
 
  
  
  
  
  
  
  
  
  
  
  
  
  
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
00H
00H
FFH
FFH
00H
00H
00H
FFH
FFH
00H
00H
0000H
0000H
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